XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 41

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Table 56: Block RAM and FIFO Switching Characteristics (Cont’d)
DSP48E1 Switching Characteristics
Table 57: DSP48E1 Switching Characteristics
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. T
11. The FIFO reset must be asserted for at least three positive clock edges.
12. When using ISE software v12.4 or later, if the RDARRDR_COLLISION_HWCONFIG attribute is set to PERFORMANCE or the block RAM
T
T
T
Reset Delays
T
T
Maximum Frequency
F
F
F
F
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T
T
T
T
RCCK_WE
RCCK_WREN
RCCK_RDEN
RCO_FLAGS
RCCK_RSTREG
MAX
MAX_CASCADE
MAX_FIFO
MAX_ECC
DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPDCK_C_CREG
DSPDCK_D_DREG
TRACE will report all of these parameters as T
T
These parameters also apply to synchronous FIFO with DO_REG = 0.
T
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
T
The ADDR setup and hold must be met when EN is asserted
possible.
T
is in single-port operation, then the faster F
RCKO_DOR
RCKO_DO
RCKO_FLAGS
RCKO_POINTERS
RCKO_DI
RCO_FLAGS
/T
Symbol
RCKC_WE
/T
/T
includes both A and B inputs as well as the parity inputs of A and B.
includes T
RCKC_RDEN
RCKC_WREN
/T
includes T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCKC_RSTREG
includes the following parameters: T
/T
/T
includes both T
Symbol
DSPCKD_C_CREG
DSPCKD_D_DREG
RCKO_DOP
RCKO_DOW
as well as the B port equivalent timing parameters.
Write Enable (WE) input (Block RAM only)
WREN FIFO inputs
RDEN FIFO inputs
Reset RST to FIFO Flags/Pointers
FIFO reset timing
Block RAM in TDP and SDP modes
(Write First and No Change modes)
Block RAM (Read First mode)
Block RAM (SDP mode)
Block RAM Cascade
(Write First and No Change modes)
Block RAM Cascade (Read First mode)
FIFO in all modes
Block RAM and FIFO in ECC configuration
, T
RCKO_RDCOUNT
RCKO_DOPR
/
MAX
RCKO_DO
, and T
for WRITE_FIRST/NO_CHANGE modes apply.
Description
and T
RCKO_AEMPTY
{A, ACIN, B, BCIN} input to {A, B}
register CLK
C input to C register CLK
D input to D register CLK
(11)
RCKO_DOPW
RCKO_WRCOUNT.
.
(12)
www.xilinx.com
(even when WE is deasserted)
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
, T
Description
RCKO_AFULL
as well as the B port equivalent timing parameters.
(10)
, T
RCKO_EMPTY
0.44/
0.47/
0.46/
0.22/
0.19
0.26
0.26
0.90
0.23
600
525
525
550
475
600
450
-3
. Otherwise, block RAM data corruption is
, T
0.47/
0.50/
0.50/
0.24/
0.25
0.27
0.27
0.98
0.24
540
475
475
490
425
400
540
Speed Grade
-2
0.25/
0.16/
0.07/
RCKO_FULL
0.27
0.20
0.31
-3
0.29/
0.19/
0.10/
0.30
0.22
0.34
0.52/
0.55/
0.55/
0.28/
, T
-2
0.35
0.30
0.30
1.10
0.26
450
400
400
400
350
450
325
-1
Speed
RCKO_RDERR
0.35/
0.22/
0.15/
0.34
0.24
0.39
-1
0.67/
0.68/
0.67/
0.31/
0.24
0.31
0.31
1.23
0.27
340
275
275
300
235
340
250
-1L
, T
0.46/
0.33/
0.24/
0.39
0.30
0.45
-1L
RCKO_WRERR.
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Units
ns
ns
ns
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