ICS97U2A845AHLFT IDT, Integrated Device Technology Inc, ICS97U2A845AHLFT Datasheet

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ICS97U2A845AHLFT

Manufacturer Part Number
ICS97U2A845AHLFT
Description
IC CLOCK DRIVER 28-CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS97U2A845AHLFT

Input
Clock
Output
SSTL-18
Frequency - Max
410MHz
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-CABGA
Frequency-max
410MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
97U2A845AHLFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS97U2A845AHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Recommended Application:
Product Description/Features:
Switching Characteristics:
Block Diagram
CLK_INC
1202—06/30/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
CLK_INT
1.8V Low-Power Wide-Range Frequency Clock Driver
FB_INC
FB_INT
10K-100k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
Double the drive of the standard 97U877 device
Low skew, low jitter PLL clock driver
1 to 5 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Period jitter: 40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
AV
OE
OS
DD
GND
Integrated
Circuit
Systems, Inc.
Powerdown
Control and
Test Logic
PLL
LD*
PLL bypass
LD* or OE
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
A
B
C
D
E
F
Ball Assignments
A
B
C
D
E
F
Pin Configuration
CK_INC
CK_INT
CLKC4
CLKT0
AGND
AVDD
1
1
28-Ball BGA
Advance Information
2
Top View
CLKC0
CLKT4
GND
GND
V
OE
2
DD
3
ICS97U2A845A
CLKC1
CLKC3
4
V
V
NB
NB
3
DD
DD
5
CLKT1
CLKT3
GND
GND
V
OS
4
DD
FB_OUTC
FB_OUTT
FB_INC
FB_INT
CLKC2
CLKT2
5

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ICS97U2A845AHLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: • Double the drive of ...

Page 2

ICS97U2A845A Advance Information Pin Descriptions ...

Page 3

Function Table ...

Page 4

ICS97U2A845A Advance Information Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . ...

Page 5

Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V High level input voltage V DC ...

Page 6

ICS97U2A845A Advance Information Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL must ...

Page 7

VDD/2 ICS97U2A845 -VDD FB_OUTC FB_OUTT X 1202—06/30/06 Parameter Measurement Information V DD ICS97U2A845 GND Figure 1. IBIS Model Output Load GND R = 10Ω 0Ω ...

Page 8

ICS97U2A845A Advance Information CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 1202—06/30/06 Parameter Measurement Information ...

Page 9

Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 1202—06/30/06 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t slr ...

Page 10

ICS97U2A845A Advance Information CK CK FBIN FBIN t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 1202—06/30/ SSC OFF SSC )dyn Figure 9. ...

Page 11

Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended ...

Page 12

ICS97U2A845A Advance Information SYMBOL Ordering Information ICS97U2A845AH(LF)-T Example: ICS XXXX y H (LF)- T 1202—06/30/06 Millimeter MIN NOM MAX 0.80 0.90 1.00 0.165 0.20 0.235 0.16 0.20 0.24 0.475 0.50 ...

Page 13

Revision History Rev. Issue Date Description 0.1 2/22/2006 Initial Release 0.2 6/30/2006 Updated Electrical Characteristics. 1202—06/30/06 ICS97U2A845A Advance Information 13 Page # - 4-5 ...

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