ICS97U2A845AHLFT IDT, Integrated Device Technology Inc, ICS97U2A845AHLFT Datasheet - Page 2

• Manufacturer Part Number: ICS97U2A845AHLFT
• Description: IC CLOCK DRIVER 28-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS97U2A845AHLFT

• Input: Clock
• Output: SSTL-18
• Frequency - Max: 410MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-CABGA
• Frequency-max: 410MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 97U2A845AHLFT

ICS97U2A845A
Advance Information
Pin Descriptions
The PLL clock buffer, ICS97U2A845A, is designed for a V
output levels. Package options include a plastic 28-ball VFBGA.
ICS97U2A845A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five
differential pair of clock outputs (CLKT[0:4], CLKC[0:4]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or V
OS is low, OE has no effect on CLKT3/CLKC3 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
The PLL in ICS97U2A845A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]).
ICS97U2A845A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U2A845A is characterized for operation from 0°C to 70°C.
1202—06/30/06
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