ICS97U2A845AHLFT IDT, Integrated Device Technology Inc, ICS97U2A845AHLFT Datasheet - Page 6

• Manufacturer Part Number: ICS97U2A845AHLFT
• Description: IC CLOCK DRIVER 28-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS97U2A845AHLFT

• Input: Clock
• Output: SSTL-18
• Frequency - Max: 410MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-CABGA
• Frequency-max: 410MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 97U2A845AHLFT

ICS97U2A845A
Advance Information
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset ( t
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK may be left floating after they have been driven low for one
complete clock cycle.
1202—06/30/06
T
Max clock frequency
Application Frequency Range
Input clock duty cycle
CLK stabilization
T
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
t
t
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
Switching Characteristics
Timing Requirements
(Ø)dyn +
jit (per) +
A
A
= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
Output to Output Skew
t
PARAMETER
t
skew(o)
(Ø)dyn +
PARAMETER
t
skew(o)
1
SYMBOL
t
t
t
SLr1(o)
t
t
t
jit(hper)
SLr1(i)
∑
∑
jit (per)
t
jit(cc+)
(Ø)dyn
jit(cc-)
SPO
skew
t
t
dis
en
(su)
t (h)
SYMBOL
2
freq
freq
T
d
STAB
tin
App
op
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
CONDITION
CONDITIONS
6
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 410
160 to 270
271 to 410
271 to 410
160 to 270
271 to 410
(MHz)
MIN
160
95
40
30.00
MIN
0.00
-40
-30
-60
-50
-50
-20
-50
0.5
1.5
2.0
1
0
0
(
Æ ), after power-up.
TYP
4.73
5.82
MAX
2.5
2.5
410
410
60
15
0
-0.50
MAX
UNITS
-40
40
30
60
50
40
50
20
50
80
60
40
30
33
MHz
MHz
8
8
4
3
µs
%
During
UNITS
MHz
v/ns
v/ns
v/ns
kHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%