IDTCV128PAG8 IDT, Integrated Device Technology Inc, IDTCV128PAG8 Datasheet - Page 10

• Manufacturer Part Number: IDTCV128PAG8
• Description: IC CLK BUFFER 1-12 DIFF 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV128PAG8

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV128PAG8

PWRDWN FUNCTIONALITY
BUFFER POWER-UP STATE DIAGRAM
IDTCV128
1-TO-12 DIFFERENTIAL CLOCK BUFFER
V
TT
_P
WR
G
0
1
D
#/P
WRDWN
Power Off
>0.25 ms
Delay
S1
S0
Normal
Float
DIF
Normal
DIF#
Float
10
BUFFER POWER-UP STATE MACHINE
NOTE:
1. The total power up latency from power on to all outputs active must be less than 1ms
(assuming a valid clock is present on CLK_IN input). If power is valid and P
de-asserted but no input clocks are present on the CLK_IN input, DIF clocks must remain
disabled. Only after valid input clocks are detected, valid power, P
with the PLL locked/stable and the DIF outputs enabled (doesn't apply to bypass mode).
State0
State1
State2
State3
State
P
WRDWN
No Input Clock
Wait for input
de-assertion
Operation
clock and
P
Normal
WRDWN
S3
S2
# Asserted
Power off
After 3.3V supply is detected to rise above 1.8-2V, the
buffer enters state1 and initiates a 0.2ms-0.3ms delay.The
total power up latency from power on to all outputs active
must be less than 1ms (assume SRC_IN is available)
Buffer waits for a valid clock on the SRC_IN input and
PD de-assertion.
Only after SRC_IN and power valid, PD de-asserted
with the current mirror stable, or PLL lock, the DIF
outputs are enabled
COMMERCIAL TEMPERATURE RANGE
#
Description
WRDWN
# de-asserted
WRDWN
(1)
is