IDTCV128PAG8 IDT, Integrated Device Technology Inc, IDTCV128PAG8 Datasheet - Page 3

• Manufacturer Part Number: IDTCV128PAG8
• Description: IC CLK BUFFER 1-12 DIFF 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV128PAG8

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV128PAG8

PIN DESCRIPTION
NOTE:
(1) The SA_2 pin shares functionality with PLL_bypass# mode
setting. The shared function restricts the device addresses that
correspond to SA_2 =0 as setting the buffer device in
PLL_Bypass#.
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV128
1-TO-12 DIFFERENTIAL CLOCK BUFFER
(1)
11-18
20-27
29-36
38-45
DIF_[9:0] & DIF_[9:0]#
V
Bit
2-9
10
19
28
37
46
CLK_IN, CLK_IN#
DIF & DIF# [11:10]
SA_2/PLL_BYPASS#
1
TT
_P
OE _10_11#
HIGH_BW#
Pin Name
OE_[9:0]#
SA_[0:1]
WRGD
FS_A
IREF
SDA
SCL
# of bits
#/P
1
8
1
8
1
8
1
8
1
8
1
WRDWN
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
I/O, OC
Type
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Start
See SMBus Address Mode table
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Description
17, 19, 20, 24, 25, 32, 33,
6, 7, 9, 10, 13, 14, 16,
35, 36, 39, 40, 42, 43
5, 8, 15, 18, 21, 26,
47, 48, 51, 52
31, 34, 41, 44
Pin #
4, 27
2, 3
53
29
28
54
30
46
45
1
0.7v Differential input
0.7 V Differential clock outputs, geared to a ratio of the input clock
0.7 V Differential clock outputs, which can be configured to be 1:1 instead of geared. Default
is geared same as 0-9 outputs.
3.3 V LVTTL active LOW input for enabling corresponding differential output clock. Clocks
3.3 V LVTTL active low input for enabling both DIF10 and 11differential output clocks. Clocks
also can be disabled via SMBus registers individually.
3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW.
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential output current
3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address.
3.3 V LVTTL input for PLLbypass and SMBus address. 0=PLLbypass mode; 1=PLL mode
3.3V LVTTL input to establish a HIGH (>200Mhz) or LOW frequency(<200Mhz) range
3.3 V LVTTL input to power up or power down the device.
3
also can be disabled via SMBus registers
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
Description
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
COMMERCIAL TEMPERATURE RANGE
first data byte (Offset data byte)
Start
See SMBus Address Mode table
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
See SMBus Address Mode table
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes)
:
Description