ICS954206BFT IDT, Integrated Device Technology Inc, ICS954206BFT Datasheet - Page 2

• Manufacturer Part Number: ICS954206BFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS954206BFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 954206BFT

Pin Description
0940—06/23/05
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
*SELPCIEX_LCDCLK#/PCI
CLK_F1
Vtt_PwrGd#/PD
VDD48
FSLA/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FSLB/TEST_MODE
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
Integrated
Circuit
Systems, Inc.
PIN NAME
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
I/O
I/O
I/O
IN
IN
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
3.3V tolerant input for CPU frequency selection. Refer to input electrical
2
DESCRIPTION
Advance Information
ICS954206B