ICS98UAE877AHLF IDT, Integrated Device Technology Inc, ICS98UAE877AHLF Datasheet

ICS98UAE877AHLF

Manufacturer Part Number

ICS98UAE877AHLF

Description

IC CLOCK DRIVER 1.8V LP 52-BGA

Manufacturer

IDT, Integrated Device Technology Inc

Type

Clock Driverr

Datasheet

1.ICS98UAE877AHLFT.pdf (16 pages)

Specifications of ICS98UAE877AHLF

Input

Clock

Output

Clock

Frequency - Max

410MHz

Voltage - Supply

1.425 V ~ 1.575 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

52-BGA

Frequency-max

410MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

98UAE877AHLF

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

ICS98UAE877AHLF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

ICS98UAE877AHLFT

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 16
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1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

Description

The PLL clock buffer, ICS98UAE877A, is designed for a

and output levels.

ICS98UAE877A is a zero delay buffer that distributes a

differential clock input pair (CLK_INT, CLK_INC) to ten

differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and

one differential pair feedback clock outputs (FB_OUTT,

FBOUTC). The clock outputs are controlled by the input

clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,

FB_INC), the LVCMOS program pins (OE, OS) and the

Analog Power input (AVDD). When OE is low, the outputs

(except FB_OUTT/FB_OUTC) are disabled while the

internal PLL continues to maintain its locked-in frequency.

OS (Output Select) is a program pin that must be tied to

GND or V

described above. When OS is low, OE has no effect on

CLKT7/CLKC7 (they are free running in addition to

FB_OUTT/FB_OUTC). When AV

turned off and bypassed for test purposes.

When both clock signals (CLK_INT, CLK_INC) are logic

low, the device will enter a low power mode. An input logic

detection circuit on the differential inputs, independent from

the input buffers, will detect the logic low level and perform

a low power state where all outputs, the feedback and the

PLL are OFF. When the inputs transition from both being

logic low to being differential signals, the PLL will be turned

back on, the inputs and outputs will be enabled and the PLL

will obtain phase lock between the feedback clock pair

(FB_INT, FB_INC) and the input clock pair (CLK_INT,

CLK_INC) within the specified stabilization time tSTAB.

The PLL in ICS98UAE877A clock driver uses the input

clocks (CLK_INT, CLK_INC) and the feedback clocks

(FB_INT, FB_INC) to provide high-performance, low-skew,

low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).

ICS98UAE877A is also able to track Spread Spectrum

Clocking (SSC) for reduced EMI.

ICS98UAE877A is available in Commercial Temperature

Range (0°C to 70°C) and Industrial Temperature Range

(-40°C to +85°C). See Ordering Information for details

1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

DDQ

of 1.5V, an AV

DDQ

. When OS is high, OE will function as

of 1.5V and differential data input

is grounded, the PLL is

Features

•

Applications

•

Switching Characteristics

•

Low skew, low jitter PLL clock driver

1 to 10 differential clock distribution

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

Auto PD when input signal is at a certain logic state

Available in 52-ball VFBGA and a 40-pin MLF

DDR2 Memory Modules / Zero Delay Board Fan Out

Provides complete DDR DIMM solution with

IDT74SSTUAE32xxx family

Period jitter:

Half-period jitter:

Output-Output Skew

Cycle-Cycle Jitter

40ps (DDR2-400/533)

30ps (DDR2-667)

60ps (DDR2-400/533)

50ps (DDR2-667)

40ps (DDR2-400/533)

30ps (DDR2-667)

40ps

ICS98UAE877A

DATASHEET

7181/3

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ICS98UAE877AHLF Summary of contents

Page 1

LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Description The PLL clock buffer, ICS98UAE877A, is designed for 1.5V 1.5V and differential data input DDQ DD and output levels. ICS98UAE877A is a zero delay buffer that distributes ...

Page 2

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Block Diagram CLK_INT CLK_INC 10K - 100K FBIN_INT FBIN_INC NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and ...

Page 3

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Pin Configurations CLKT1 CLKT0 CLKC0 CLKC5 B CLKC1 GND GND GND C CLKC2 GND NB D ...

Page 4

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Pin Descriptions Terminal Name AGND AV DD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND V DDQ CLKT[0:9] CLKC[0:9] NB 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Description Analog Ground Analog Power Clock ...

Page 5

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Function Table Inputs GND H GND H GND L GND L 1.5V (nom) L 1.5V (nom) L 1.5V (nom) H 1.5V (nom) H 1.5V (nom) X 1.5V (nom) X ...

Page 6

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C, Industrial Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...

Page 7

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Recommended Operating Conditions Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C, Industrial Symbol Parameter Supply Voltage V DDQ LOW - Level Input V ...

Page 8

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Timing Requirements Over Recommended Operating Free-Air Temperature Range Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C, Industrial Symbol Parameter freq Max Clock Frequency OP freq Application Frequency ...

Page 9

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Switching Characteristics Over Recommended Free Air Operating Range Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C, Industrial Symbol Parameter t Output Enable Time EN t Output ...

Page 10

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Parameter Measurement Information ICS98UAE877A Yx, FB_OUTC Yx, FB_OUTT 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER V DD ICS98UAE877A GND Figure 1: IBIS Model Output Load GND C = ...

Page 11

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER CLK_INC CLK_INT CLK_INC CLK_INT Yx Yx Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER COMMERCIAL TEMPERATURE GRADE ...

Page 12

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Yx, FB_OUTC Yx, FB_OUTT 20% Clock Inputs and outputs 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER t t JIT(HPER_n) JIT(HPER_n+ JIT(HPER) JIT(HPER_n) 2xfo Figure 7: Half-Period Jitter ...

Page 13

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER CLK CLK FB_IN FB_IN t( )dyn 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER t( ) SSC OFF SSC ON t( )dyn Figure 9: Dynamic Phase Offset 50% V ...

Page 14

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER VIA 1 CARD V DDQ GND VIA CARD *Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and ...

Page 15

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Ordering Information XXX XX ICSS98UAE Device Type Package 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER X X Shipping Shipping Carrier Carrier T Tape and Reel Blank 0°C to +70°C (Commercial) I -40°C to +85°C ...

Page 16

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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