ICS9EX21801AKLFT IDT, Integrated Device Technology Inc, ICS9EX21801AKLFT Datasheet - Page 3

• Manufacturer Part Number: ICS9EX21801AKLFT
• Description: IC FANOUT BUFF DIFF 20-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EX21801AKLFT

• Input: *
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9EX21801AKLFT

Pin Description
IDT
PIN #
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TM
1
2
3
4
5
6
7
8
9
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
VDD
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
OE12#
DIF_12
DIF_12#
GND
VDD
DIF_13
DIF_13#
OE13#
DIF_14
DIF_14#
OE14#
DIF_15
DIF_15#
VDD
OE15_17#
DIF_16
DIF_16#
DIF_17
DIF_17#
IREF
GNDA
VDDA
CLKA_IN
CLKA_IN#
GND
CLKB_IN
CLKB_IN#
VDD
OE_01234#
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply, nominal 3.3V
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 15, 16 and 17
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475
ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
True Input for differential reference clock.
Complement Input for differential reference clock.
Ground pin.
True Input for differential reference clock.
Complement Input for differential reference clock.
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
3
DESCRIPTION
1463B — 01/20/10
Datasheet