ICS9EX21801AKLFT IDT, Integrated Device Technology Inc, ICS9EX21801AKLFT Datasheet - Page 4

• Manufacturer Part Number: ICS9EX21801AKLFT
• Description: IC FANOUT BUFF DIFF 20-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EX21801AKLFT

• Input: *
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9EX21801AKLFT

Pin Description (continued)
IDT
PIN #
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TM
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
DIF_0
DIF_0#
DIF_1
DIF_1#
DIF_2
DIF_2#
VDD
GND
DIF_3
DIF_3#
DIF_4
DIF_4#
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
100M_133M#
HIBW_BYPM_LOBW#
SMBCLK
SMBDAT
SMB_A1
SMB_A0
SEL_A_B#
CKPWRGD/PD#
DIF_9
DIF_9#
OE9#
PIN NAME
PIN TYPE
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Input to select operating frequency
0 = 133MHz (QPI), 1 = 100.00MHz (PCIe Gen2)
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
SMBus address bit 1
SMBus address bit 0 (LSB)
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling
edge.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
4
DESCRIPTION
1463B — 01/20/10
Datasheet