ICS9EX21801AKLFT IDT, Integrated Device Technology Inc, ICS9EX21801AKLFT Datasheet - Page 5

• Manufacturer Part Number: ICS9EX21801AKLFT
• Description: IC FANOUT BUFF DIFF 20-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EX21801AKLFT

• Input: *
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9EX21801AKLFT

IDT
T
1
2
3
Absolute Maximum Ratings
Ambient Operating Temp
Electrical Characteristics - Input/Supply/Common Output Parameters
Guaranteed by design and characterization, not 100% tested in production.
Time from deassertion until outputs are >200 mV
For which spread spectrum tracking error spec will be met.
A
Analog Supply Current
Modulation Frequency
Digital Supply Current
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Storage Temperature
Input ESD protection
TM
= 0 - 70°C; Supply Voltage V
Analog Powerdown
Input High Voltage
3.3V Logic Supply
Case Temperature
Input High Current
Digital Powerdown
Input Low Voltage
Allowable Spread
3.3V Core Supply
Input Low Current
Input Frequency
Clk Stabilization
Pin Inductance
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
PARAMETER
PARAMETER
OE# Latency
Capacitance
Tdrive_PD
Voltage
Voltage
Current
Current
Trise
Tfall
Tambient
SYMBOL
SYMBOL
ESD prot
I
I
F
VDD_A
Tcase
DD3.3DPD
DD3.3APD
t
I
I
t
T
iBYPASS
LATOE#
DD3.3D
DD3.3A
C
VDD
F
DRVPD
f
L
V
V
I
I
C
DD
STAB
MOD
Ts
I
IL1
IL2
iPLL
OUT
t
t
IH
pin
F
R
IH
IL
IN
= 3.3 V +/-5%
V
clock stabilization or de-assertion of
IN
From V
V
DIF stop after OE# deassertion
= 0 V; Inputs with pull-up resistors
IN
DIF start after OE# assertion
all differential pairs tri-stated
all differential pairs tri-stated
Full Active, C
Full Active, C
= 0 V; Inputs with no pull-up
Output pin capacitance
DIF output enable after
Triangular Modulation
DD
Human Body Model
Rise time of OE#
PD# to 1st clock
Fall time of OE#
PD de-assertion
Power-Up and after input
CONDITIONS
CONDITIONS
Bypass Mode
3.3 V +/-5%
3.3 V +/-5%
Logic Inputs
PLL Mode
V
resistors
IN
= V
L
L
= Full load;
= Full load;
DD
5
GND - 0.5
GND - 0.5
GND - 0.3
2000
-200
MIN
MIN
-65
1.5
80
33
30
-5
-5
2
4
0
TYP
TYP
V
V
V
DD
DD
DD
MAX
MAX
150
115
450
150
400
300
0.8
40
15
20
33
12
70
+ 0.5
+ 0.5
+ 0.3
5
7
5
6
1
5
5
1463B — 01/20/10
Datasheet
UNITS Notes
UNITS NOTES
cycles
MHz
MHz
kHz
mA
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
us
ns
ns
°
°C
°C
V
V
V
V
V
C
1,3
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1