ICS932S208DFLF IDT, Integrated Device Technology Inc, ICS932S208DFLF Datasheet - Page 15

• Manufacturer Part Number: ICS932S208DFLF
• Description: IC TIMING HUB CTRL PROGR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr
• Series: TCH™r

Specifications of ICS932S208DFLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 200MHz
• Number Of Elements: 2
• Supply Current: 350mA
• Pll Input Freq (min): 14.31818MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SSOP
• Output Frequency Range: 33.33 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 932S208DFLF

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI_STOP# Assertion (transition from '1' to '0')
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
IDT
PCI Stop Functionality
PCI_STOP# - De-assertion
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
P
ICS932S208
Programmable Timing Control Hub
TM
C
_ I
Programmable Timing Control Hub
S
0
1
T
O
P
#
N
N
C
r o
r o
P
m
m
U
l a
l a
PCIF[2:0] 33MHz
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
PCI[6:0] 33MHz
SRC# 100MHz
N
N
C
SRC# 100MHz
SRC 100MHz
SRC 100MHz
PCI_STOP#
r o
r o
P
PCI_STOP#
U
m
m
l a
l a
#
TM
for Next Gen P4
TM
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N
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for Next Gen P4
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6
Tsu
Tsu
N
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L
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R
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TM
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w
Processor
#
l a
Tdrive_SRC
TM
Processor
6
6
3
6
6
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M
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6
H
H
6
15
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P
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C
3
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w
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I C
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4
4
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8
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4
3 .
3 .
R
1
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0743G—01/26/10