ICS932S208DFLF IDT, Integrated Device Technology Inc, ICS932S208DFLF Datasheet - Page 5

• Manufacturer Part Number: ICS932S208DFLF
• Description: IC TIMING HUB CTRL PROGR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr
• Series: TCH™r

Specifications of ICS932S208DFLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 200MHz
• Number Of Elements: 2
• Supply Current: 350mA
• Pll Input Freq (min): 14.31818MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SSOP
• Output Frequency Range: 33.33 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 932S208DFLF

Absolute Maximum Ratings
IDT
T
1
2
3
Electrical Characteristics - Input/Supply/Common Output Parameters
Operating Supply Current
Tambient
ppm frequency accuracy on PLL outputs.
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
ESD prot
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
A
Symbol
VDD_In
VDD_A
ICS932S208
Programmable Timing Control Hub
Modulation Frequency
Tcase
TM
= 0 - 70°C; Supply Voltage V
Powerdown Current
Tdrive_CPU_Stop#
Input Capacitance
Input High Voltage
Input High Current
Trise_CPU_Stop#
Input MID Voltage
Input Low Voltage
Input Low Current
Clk Stabilization
Tfall_CPU_Stop#
Ts
Input Frequency
Programmable Timing Control Hub
Pin Inductance
PARAMETER
Tdrive_SRC
Tdrive_PD#
Trise_Pd#
Tfall_Pd#
3.3V Logic Input Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
1,2
Input ESD protection
1
3
human body model
Case Temperature
1
Parameter
SYMBOL
I
I
DD3.3OP
DD3.3PD
T
C
V
C
DD
L
C
V
V
I
I
STAB
I
F
IL1
IL2
OUT
MID
IH
INX
pin
IH
IL
IN
i
= 3.3 V +/-5%
TM
for Next Gen P4
TM
for Next Gen P4
V
assertion of PD# to 1st clock
IN
V
all differential pairs tri-stated
From V
Full Active, C
IN
CPU_Stop# de-assertion
= 0 V; Inputs with no pull-up
SRC output enable after
CPU output enable after
CPU output enable after
PCI_Stop# de-assertion
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
all diff pairs driven
PD# de-assertion
PD# rise time of
PD# rise time of
PD# fall time of
PD# fall time of
CONDITIONS
X1 & X2 pins
Logic Inputs
DD
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
V
TM
resistors
resistors
DD
GND - 0.5
Power-Up or de-
IN
Processor
= 3.3 V
= V
2000
Min
TM
-65
L
0
= Full load;
DD
Processor
5
V
V
DD
DD
Max
150
115
+ 0.5V
+ 0.5V
70
V
SS
-200
MIN
30
-5
-5
2
1
- 0.3
14.31818
Units
TYP
°C
°C
°
V
V
V
C
V
DD
MAX
350
300
1.8
0.8
1.8
35
12
33
15
10
5
7
5
6
5
5
5
5
5
+ 0.3
UNITS NOTES
MHz
kHz
mA
mA
mA
uA
uA
nH
ms
uA
pF
pF
pF
ns
us
ns
ns
us
ns
ns
V
V
V
0743G—01/26/10
1,2
3
1
1
1
1
1
1
1
1
2
1
1
2