TUA 6030 Infineon Technologies, TUA 6030 Datasheet - Page 39

• Manufacturer Part Number: TUA 6030
• Description: IC MIXER/OSC/PLL DIGITAL TSSOP38
• Manufacturer: Infineon Technologies

Specifications of TUA 6030

• Package / Case: 38-TSSOP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Bus Type: I2C
• Maximum Agc: 0.5 dB
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 44.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 8 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 10 C
• Maximum Operating Temperature: + 125 C
• Packages: PG-TSSOP-38
• Vs (min): 4.5 V
• Vs (max): 5.5 V
• Icc (max): 66.0 mA
• Esd Protection (max): 2.0 kV
• Mounting: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000012954; TUA6030XT

Wireless Components
Table 5-4 Bit Allocation Read / Write
Name
Write Data
Address Byte
Divider Byte 1
Divider Byte 2
Control byte
Bandswitch byte
Auxiliary byte
Read data
Address byte
Status byte
Table 5-5 Description of Symbols
Symbol
A
MA0, MA1
N14 to N0
CP
T0, T1, T2
RSA, RSB
OS
P0, P1, P2, P3
P4, P5, P6, P7
ATC
1). AB replaces BB when T2, T1, T0 = 0, 1, 1,
1).
5.2 Programming
ADB
DB1
DB2
CB
BB
AB
ADB
SB
Byte
Acknowledge
Address selection bits,
programmable divider bits:
N = 2
charge pump current bit:
bit = 0: charge pump current = 60 µA
bit = 1: charge pump current = 280µA (default)
test bits,
reference divider bits,
tuning amplifier control bit:
bit = 0: enable V
bit = 1: disable V
PNP ports control bits
bit = 0: Port is inactive, high impedance state (default)
bit = 1: Port is active, V
NPN ports control bits
bit = 0: Port is inactive, high impedance state (default)
bit = 1: Port is active, V
AGC time constant bit
bit = 0: I
bit = 1: I
MSB
POR
ATC
14
N7
P7
1
0
1
1
x N14 + 2
AGC
AGC
see Table 5-7 Test modes on page 40
=220nA; t=2s with C=160nF (default)
=9µA; t=50ms with C=160nF
bit6
N14
AL2
CP
N6
P6
FL
1
1
T
T
13
see Table 5-7 Test modes on page 40
(default)
x N13 + ..... + 2
see Table 5-8 Reference divider ratios on page 40
see Table 5-6 Address selection on page 40
OUT
OUT
bit5
N13
AL1
5 - 39
N5
P5
T2
0
0
1
= V
= V
CC
CESAT
bit4
N12
AL0
N4
P4
-V
T1
0
0
1
CESAT
Description
3
Bits
x N3 + 2
AGC
bit3
N11
N3
P3
T0
0
0
0
2
x N2 + 2
MA1
RSA
MA1
bit2
N10
N2
P2
A2
0
1
TUA6030, TUA6032
xN1 + N0
MA0
RSB
MA0
bit1
N9
N1
P1
A1
Specification, July 2001
0
W=0
W=1
LSB
OS
N8
N0
P0
A0
R/
R/
0
Reference
Ack
A
A
A
A
A
A
A
A