ICS8305AGILF IDT, Integrated Device Technology Inc, ICS8305AGILF Datasheet - Page 11

• Manufacturer Part Number: ICS8305AGILF
• Description: IC CLK FAN BUFF MUX 2:4 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8305AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1947-5; 8305AGILF; ICS8305AGILF

IDT™ / ICS™ LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER
F
8305AGI
F
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
PP
IGURE
IGURE
IFFERENTIAL
3.3V
and V
R5,R6 locate near the driver pin.
3.3V
LVPECL
3C. H
3A. H
3E. H
1.8V
CMR
LVPECL
R5
100 - 200
input requirements. Figures 3A to 3E show inter-
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
ICS H
3.3V LVPECL D
I
Integrated
Circuit
Systems, Inc.
I
P
I
P
P
C
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
R6
100 - 200
C
Zo = 50 Ohm
Zo = 50 Ohm
C
C
I
P
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
ER
C
I
S CLK/
S CLK/
NPUT
LOCK
S CLK/
RIVER
R1
50
S LVHSTL D
RIVER WITH
3.3V
R3
125
C1
C2
I
R1
84
NTERFACE
SWING
N
N
N
CLK I
CLK I
CLK I
3.3V
R3
125
R2
50
R4
125
R1
84
R2
84
and V
R4
125
CLK
nCLK
R2
84
NPUT
AC C
NPUT
NPUT
CLK
nCLK
3.3V
OH
3.3V
RIVER
HiPerClockS
Input
must meet the
www.icst.com/products/hiperclocks.html
HiPerClockS
Input
D
D
D
OUPLE
CLK
nCLK
RIVEN BY
RIVEN BY
RIVEN BY
3.3V
HiPerClockS
Input
LVCMOS-
L
OW
11
11
F
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
S
IGURE
IGURE
KEW
3.3V
3.3V
TO
3D. H
3B. H
LVDS_Driv er
, 1-
LVPECL
-LVCMOS/LVTTL F
3.3V LVPECL D
3.3V LVDS D
TO
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
-4, M
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
ULTIPLEXED
S CLK/
S CLK/
RIVER
R1
50
RIVER
R3
50
N
N
R2
50
CLK I
CLK I
R1
100
CLK
nCLK
ANOUT
3.3V
D
NPUT
NPUT
HiPerClockS
IFFERENTIAL
Input
REV. B MAY 19, 2005
CLK
nCLK
D
D
3.3V
B
RIVEN BY
RIVEN BY
Receiv er
UFFER
ICS8305I
TSD
/