ICS8543BGLF IDT, Integrated Device Technology Inc, ICS8543BGLF Datasheet - Page 12

• Manufacturer Part Number: ICS8543BGLF
• Description: IC FANOUT BUFF DIFF-LVDS 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8543BGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 800MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 800MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 800MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1186; 800-1186-5; 800-1186; 8543BGLF

ICS8543 Data Sheet
3.3V LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
V
for the PCLK/nPCLK input driven by the most common driver types.
Figure 4A. PCLK/nPCLK Input Driven by a CML Driver
Figure 4C. PCLK/nPCLK Input Driven by a
Figure 4E. PCLK/nPCLK Input Driven by a
ICS8543BG REVISION E DECEMBER 17, 2010
CMR
3.3V
input requirements. Figures 4A to 4E show interface examples
2.5V
3.3V
CML
LVPECL
SSTL
3.3V LVPECL Driver
2.5V SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
SWING
and V
R3
120
R3
125Ω
2.5V
R1
50Ω
3.3V
R1
120
3.3V
R1
84Ω
OH
R4
120
R4
125Ω
must meet the V
R2
50Ω
R2
120
R2
84Ω
PCLK
nPCLK
PCLK
nPCLK
PCLK
nPCLK
3.3V
3.3V
3.3V
LVPECL
Input
LVPECL
Input
LVPECL
Input
PP
and
12
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 4B. PCLK/nPCLK Input Driven by a
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V
3.3V LVPECL
3.3V
CML Built-In Pullup
R5
100Ω - 200Ω
Built-In Pullup CML Driver
3.3V LVPECL Driver with AC Couple
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
R6
100Ω - 200Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
C1
C2
©2010 Integrated Device Technology, Inc.
R1
50Ω
R1
100Ω
R2
50Ω
PCLK
nPCLK
3.3V
PCLK
VBB
nPCLK
LVPECL
Input
3.3V
LVPECL
Input