MPC9600AE IDT, Integrated Device Technology Inc, MPC9600AE Datasheet - Page 7

• Manufacturer Part Number: MPC9600AE
• Description: IC PLL CLK DRIVER LV 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC9600AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 200MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 16.67MHz
• Pll Input Freq (max): 50MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming the MPC9600
several divider modes. Additionally the external feedback of the
device allows for flexibility in establishing various input to output
frequency relationships. The selectable feedback divider of the
three output groups allows the user to configure the device for 1:2,
1:3, 1:4 and 1:6 input:output frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
illustrates the various output configurations, the table describes
the outputs using the input clock frequency CLK as a reference.
IDT™ / ICS™ 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
MPC9600
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
The MPC9600 clock driver outputs can be configured into
Table 8. Output Frequency Relationship
1. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.
FSEL_FB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Configuration Inputs
FSELA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSELC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(1)
APPLICATIONS INFORMATION
for QFB Connected to FB_IN
Input Frequency
16.67–33.33
Range CLK
25.0–50.0
Table 8
[MHz]
7
relationship, in addition, it must be ensured that the VCO will be
stable given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 50 MHz to 200 MHz while the
VCO frequency range is specified from 200 MHz to 400 MHz and
should not be exceeded for stable operation.
2•CLK
2•CLK
2•CLK
3•CLK
3•CLK
3•CLK
3•CLK
4•CLK
4•CLK
4•CLK
4•CLK
2•CLK (50.0–100)
6•CLK
6•CLK
6•CLK
6•CLK
Ratio, QAx [MHz]
The feedback divider division settings establish the output
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
Output Frequency Ratio and Range
2•CLK
2•CLK
2•CLK
2•CLK
3•CLK
3•CLK
3•CLK
3•CLK
4•CLK
4•CLK
4•CLK
6•CLK
6•CLK
6•CLK
4•CLK
6•CLK
Ratio, QBx [MHz]
MPC9600 REV. 5 NOVEMBER 10, 2008
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
2•CLK
2•CLK
2•CLK
2•CLK
3•CLK
3•CLK
3•CLK
3•CLK
4•CLK
4•CLK
4•CLK
6•CLK
6•CLK
6•CLK
4•CLK
6•CLK
Ratio, QCx [MHz]
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(50.0–100)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)
(100–200)