MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 12

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from
Table 12. Confidence Factor CF
layout and can be used to fine-tune the effective delay
through each device.
offset and I/O jitter, using
maximum I/O jitter and the specified t
the input reference frequency results in a precise timing
performance analysis.
factor of 99.7% (± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of –455 ps to +455 ps relative to CCLK (PLL
feedback = ÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps rms max., static
phase offset t
t
t
SK(PP)
SK(PP)
Due to the statistical nature of I/O jitter a RMS value (1 σ)
The feedback trace delay is determined by the board
Due to the frequency dependence of the static phase
In the following example calculation an I/O jitter confidence
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
160
140
120
100
CF
80
60
40
20
0
200
= [-166ps...166ps] + [-250ps...250ps] +
= [-455ps...455ps] + t
[(13ps @ –3)...(13ps @ 3)] + t
FB=÷32
FB=÷4
(∅)
250
Figure 9. MPC9772 I/O Jitter
= ± 166 ps):
Max. I/O Phase Jitter versus Frequency
FB=÷16
Parameter: PLL Feedback Divider FB
FB=÷8
Probability of Clock Edge
300
VCO Frequency [MHz]
within the Distribution
Figure 9
Table
PD, LINE(FB)
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
12.
350
to
(∅
Figure 11
)
parameter relative to
PD, LINE(FB)
400
to predict a
450
480
12
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50 Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9772 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines.
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC9772 clock driver is
effectively doubled due to its capability to drive multiple lines.
The MPC9772 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
120
100
140
120
100
80
60
40
20
80
60
40
20
0
200
0
200
FB=÷12
Figure 10. MPC9772 I/O Jitter
Figure 11. MPC9772 I/O Jitter
Max. I/O Phase Jitter versus Frequency
250
FB=÷24
Parameter: PLL Feedback Divider FB
250
FB=÷6
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
FB=÷20
FB=÷10
FB=÷40
300
VCO Frequency [MHz]
VCO Frequency [MHz]
300
CC
÷2.
MPC9772 REV 6 FEBRUARY 7, 2007
350
350
400
400
Figure 12
450
450
480
480