MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 13

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9772 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests the dual line driving
need not be used exclusively to maintain the tight
output-to-output skew of the MPC9772. The output waveform
in
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36 Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
unity reflection coefficient, to 2.6 V. It will then increment
In
In
Figure 13
At the load end the voltage will double, due to the near
The waveform plots in
Figure 12. Single versus Dual Transmission Lines
V
Z
R
R
V
L
0
L
S
0
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18+17+25)
= 1.31 V
MPC9772
MPC9772
Output
Output
Buffer
14Ω
Buffer
14Ω
S
shows a step in the waveform, this step is
(Z
0
÷ (R
S
R
R
R
+R
S
S
S
= 36 Ω
= 36 Ω
= 36 Ω
Figure 13
0
Generator
Z = 50Ω
+Z
Pulse
0
))
Z
Z
Z
show the simulation
O
O
O
= 50 Ω
= 50 Ω
= 50Ω
Figure 15. CCLK MPC9772 AC Test Reference
Z
O
R
= 50Ω
T
= 50Ω
OutA
OutB0
OutB1
V
TT
MPC9772 DUT
13
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 14. Optimized Dual Line Termination
Figure 13. Single versus Dual Waveforms
MPC9772
Output
14Ω
Figure 14
Buffer
t
2
In
D
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
= 3.8956
OutA
Z
O
4
= 50Ω
should be used. In this case the series
R
25 Ω = 25 Ω
R
S
S
R
= 22 Ω
= 22 Ω
6
T
= 50Ω
Time (ns)
t
MPC9772 REV 6 FEBRUARY 7, 2007
D
= 3.9386
OutB
V
8
TT
Z
Z
O
O
= 50 Ω
= 50 Ω
10
12
14