MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 14

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a single
device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 16. Output-to-Output Skew t
Figure 18. Output Duty Cycle (DC)
Figure 20. Cycle-to-Cycle Jitter
T
N
t
P
T
N+1
T
0
DC = t
t
SK(O)
P
/T
0
T
Figure 22. Output Transition Time Test Reference
x 100%
JIT(CC)
= |T
t
F
N
SK(O)
-T
N+1
V
V
GND
CC
CC
|
V
V
GND
V
V
GND
÷2
CC
CC
CC
CC
÷2
÷2
14
t
R
The deviation in cycle time of a signal with respect to the ideal period over a
random sample of cycles
CCLKx
FB_IN
Figure 17. Propagation Delay (t
The deviation in t
random sample of cycles
V
CCLKx
CC
FB_IN
0.55
2.4
=3.3 V
T
0
0
Offset) Test Reference
Figure 21. Period Jitter
t
for a controlled edge with respect to a t
(∅)
Figure 19. I/O Jitter
MPC9772 REV 6 FEBRUARY 7, 2007
T
T
JIT(PER)
JIT(∅)
(∅)
= |T
, Static Phase
= |T
0
-T
N
-1/f
1
mean|
0
0
|
mean in a
V
V
GND
V
V
GND
CC
CC
CC
CC
÷2
÷2