MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 14

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
8.
The lock indicator pin (LOCK) will reliably indicate a
phase-locked condition at SYNC input frequencies
down to 10 MHz. At frequencies below 10 MHz, the
frequency of correction pulses going into the phase
detector form the SYNC and FEEDBACK pins may not
be sufficient to allow the lock indicator circuitry to
Back, Including Process and Voltage Variation @ 25°C
Back, Including Process and Voltage Variation @ 25°C
t
PD
t
PD
–0.50
–0.75
–1.00
–1.25
–1.50
versus Frequency Variation for Q/2 Output Fed
(with 1.0 MΩ Resistor Tied to Analog V
versus Frequency Variation for Q/2 Output Fed
(with 1.0 MΩ Resistor Tied to Analog GND)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.5
2.5
5.0
5.0
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
Figure 5a
Figure 5c
7.5
7.5
10.0
10.0
12.5
12.5
15.0
15.0
CC
)
17.5
17.5
Figure 5. Graphs
14
accurately predict a phase-locked condition. The
MC88915T is guaranteed to provide stable phase-
locked operation down to the appropriate minimum
input frequency given in
LOCK pin may be LOW at frequencies below 10 MHz.
Back, Including Process and Voltage Variation @ 25°C
Back, Including Process and Voltage Variation @ 25°C
t
t
PD
PD
–0.5
–1.0
–1.5
–2.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
versus Frequency Variation for Q4 Output Fed
versus Frequency Variation for Q4 Output Fed
(with 1.0 MΩ Resistor Tied to Analog GND)
(with 1.0 MΩ Resistor Tied to Analog V
2.5
0
5.0
7.5
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
5
10.0
Table
12.5
Figure 5b
Figure 5d
10
15.0
22, even though the
17.5
15
MC88915TREV 7 JULY 10, 2007
20.0
25.0
20
22.5
CC
)
27.5
25