MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 2

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
Table 1. Pin Summary
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
FEEDBACK
FREQ_SEL
Pin Name
V
REF_SEL
SYNC[0]
SYNC[1]
OE/RST
PLL_EN
CC
Q(0–4)
LOCK
2x_Q
RC1
Q/2
Q5
, GND
Number
11
1
1
1
1
1
1
5
1
1
1
1
1
1
FEEDBACK
REF_SEL
GND(AN)
SYNC[0]
V
SYNC[1]
CC
Figure 1. Pinout: 28-Lead PLCC (Top View)
(AN)
Output
Output
Output
Output
Output
RC1
Input
Input
Input
Input
Input
Input
Input
Input
I/O
FREQ_SEL GND Q0 V
OE/RST V
5
6
7
8
9
10
11
12
4
Reference clock input
Reference clock input
Chooses reference between SYNC[0] and SYNC[1]
Doubles VCO internal frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to SYNC)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output (Q) frequency ÷ 2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output enable/asynchronous reset (active low)
Disables phase-lock for low frequency testing
Power and ground pins (note pins 8 and 10 are “analog” supply pins
for internal PLL only)
13 14 15 16
3
CC
Q5 GND Q4 V
2
1
CC
2
28 27 26
Q1 GND PLL_EN
17 18
CC
2X_Q
25
24
23
22
21
20
19
Q/2
GND
Q3
V
Q2
GND
LOCK
CC
Function
MC88915TREV 7 JULY 10, 2007