MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 18

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
MC88915T System Level Testing Functionality
version of the MC88915T to ease system board testing.
Bringing the OE/RST pin low will put all outputs (except for
LOCK) into the high impedance state. As long as the PLL_EN
pin is low, the Q0–Q4, Q5, and the Q/2 outputs will remain in
the low state after the OE/RST until a falling SYNC edge is
seen. The 2X_Q output is the inverse of the SYNC signal in
this mode. If the 3-state functionality is used, a pull-up or pull-
down resistor must be tied to the FEEDBACK input pin to
prevent it from floating when the fed back output goes into
high impedance.
Three-state functionality was added to the 100 MHz
Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T
SYSTEM
CLOCK
SOURCE
for Frequency Multiplication and Low Board-to-Board Skew
AT POINT OF USE
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
CLOCK
@ f
MC88915T
MC88915T
PLL
PLL
MEMORY
CARDS
MC88915T
2f
2f
PLL
18
directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly
driven by the SYNC input (per the block diagram). This mode
can also be used for low frequency board testing.
NOTE: If the outputs are put into 3-state during normal PLL
2f
With the PLL_EN pin low the selected SNC signal is gated
CMMU
CMMU
CMMU
CMMU
CPU
CPU
CONTROL
MEMORY
AT POINT OF USE
operation, the loop will be broken and phase-lock
will be lost. It will take a maximum of 10 ms (t
spec) to regain phase-lock after the OE/RST pin
goes back high.
CLOCK @ 2f
CMMU
CMMU
CMMU
CMMU
CMMU
CMMU
CARD
CARD
CPU
CPU
MC88915TREV 7 JULY 10, 2007
LOCK