STW81102ATR STMicroelectronics, STW81102ATR Datasheet - Page 29

• Manufacturer Part Number: STW81102ATR
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizerr

Specifications of STW81102ATR

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.65GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STW81102
6.1.5
6.1.6
6.1.7
Single-byte write mode
Following a START condition, the master sends a device select code with the RW bit set to
0. The STW81102 sends an acknowledge and waits for the 1-byte internal sub-address that
provides access to the internal registers.
After receiving the sub-address internal byte, the STW81102 again responds with an
acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE
register, a single-byte write with sub-address 04H changes the CONTROL register, and so
on.
Table 11.
Multi-byte write mode
The multi-byte write mode can start from any internal address. The master sends the data
bytes, and each one is acknowledged. The master then terminates the transfer by
generating a STOP condition.
The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H
and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H),
and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81102
registers.
Table 12.
Current byte address read mode
In the current byte address read mode, following a START condition, the master sends the
device address with the RW bit set to 1. Note that no sub-address is needed since there is
only one read register. The STW81102 acknowledges this and outputs the data byte. The
master does not acknowledge the received byte, and terminates the transfer with a STOP
condition.
Table 13.
S
S
S
1100A
1100A
1100 A
2
A
Single-byte write mode
Multi-byte write mode
Current byte address read mode
1
2
A
A
1
0
A
2
0
A
0
1
A
ack
0
0
sub-address byte
ack
1
ack
sub-address byte
ack
DATA IN
DATA OUT
ack
ack
....
DATA IN
DATA IN ack
I
2
C bus interface
No ack
ack
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P
P
P