ICS843002AKI-40LF IDT, Integrated Device Technology Inc, ICS843002AKI-40LF Datasheet

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ICS843002AKI-40LF

Manufacturer Part Number
ICS843002AKI-40LF
Description
IC SYNTHESIZER LVPECL 32-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™, FemtoClock®r
Type
Clock Generator, Clock Synchronizer, Frequency Translator, Jitter Attenuator, Multiplexerr
Datasheet

Specifications of ICS843002AKI-40LF

Pll
Yes with Bypass
Input
HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTLL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
3:2
Differential - Input:output
Yes/Yes
Frequency - Max
175MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN
Frequency-max
175MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
843002AKI-40LF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS843002AKI-40LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS843002AKI-40LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
175MHZ, FEMTOCLOCK
SONET/SDH JITTER ATTENUATOR
General Description
where jitter attenuation and frequency translation is needed. The
device contains two internal PLL stages that are cascaded in
series. The first PLL stage uses a VCXO which is optimized to
provide reference clock jitter attenuation and to be jitter tolerant,
and to provide a stable reference clock for the 2nd PLL stage
(typically 19.44MHz). The second PLL stage provides additional
frequency multiplication (x32), and it maintains low output jitter by
using a low phase noise FemtoClock VCO. PLL multiplication
ratios are selected from internal lookup tables using device input
selection pins. The device performance and the PLL multiplication
ratios are optimized to support non-FEC (non-Forward Error
Correction) SONET/SDH applications with rates up to OC-48
(SONET) or STM-16 (SDH). The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given line card
application.
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Typical ICS843002I-40 configuration in SONET/SDH Systems:
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
The ICS843002I-40 includes two clock input ports. Each one can
HiPerClockS™
ICS
VCXO 19.44MHz crystal
Loop bandwidth: 50Hz - 250Hz
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
The ICS843002I-40 is a member of the
HiperClockS™ family of high performance clock
solutions from IDT. The ICS843002I-40 is a PLL
based synchronous clock generator that is
optimized for SONET/SDH line card applications
TM
VCXO BASED
1
Features
Two Differential LVPECL outputs
Selectable CLKx, nCLKx differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Maximum output frequency: 175MHz
FemtoClock VCO frequency range: 560MHz - 700MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CLK_SEL
Pin Assignment
nCLK0
5mm x 5mm x 0.925mm package body
CLK0
ISET
LF1
LF0
V
CC
nc
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32-Lead VFQFN
ICS843002I-40
K Package
ICS843002AKI-40 REV. B APRIL 27, 2009
Top View
ICS843002I-40
24
23
22
21
20
19
18
17
LOR0
LOR1
V
nQB
QB
V
nc
V
CCO_LVPECL
CCO_LVCMOS
EE

Related parts for ICS843002AKI-40LF

ICS843002AKI-40LF Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages CLK_SEL 1 ICS843002I-40 Pin Assignment LF1 1 24 LF0 2 23 ISET CLK0 nCLK0 ICS843002I-40 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS843002AKI-40 REV. B APRIL 27, 2009 LOR0 LOR1 nc V CCO_LVCMOS V CCO_LVPECL nQB ...

Page 2

... MHz External Pullable Loop xtal Components LF0 LF1 Charge Pump VCXO 19.44 MHz and Loop Filter Divide by 32 622.08 MHz C0 Divider = 4, 8, 32, or HiZ 111 111 C1 Divider = 4, 8, 32, or HiZ ICS843002AKI-40 REV. B APRIL 27, 2009 V CCO_LVPECL QA nQA 2 QA_SEL1:0 QB nQB 2 QB_SEL1:0 ...

Page 3

... Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B. Crystal oscillator interface. The XTAL_IN is the input. Input XTAL_OUT is the output. Test Conditions 3 /2 bias voltage when left floating bias voltage when left floating. CC Minimum Typical Maximum ICS843002AKI-40 REV. B APRIL 27, 2009 Units pF Ω k Ω k ...

Page 4

... IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Function R_SEL0 R Divider Value or State 0 ÷1 1 ÷2 0 ÷4 1 ÷8 0 ÷16 1 ÷32 0 bypass VCXO PLL 1 bypass VCXO and FemtoClock PLLs Function Output Divider Value or State Output QX/nQX (High-Impedance) ÷32 ÷8 ÷4 4 ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 5

... CCO_LVCMOS 50mA 100mA 37°C/W (0 mps) -65°C to 150°C = 3.3V±5 CCO_LVCMOS, CCO_LVPECL Test Conditions Minimum 3.135 V – 0.15 CC 3.135 2.375 5 + 0.5V = 3.3V±5% or 2.5V±5 0V, EE Typical Maximum Units 3.3 3.465 V 3 3.3 3.465 V 2.5 2.625 V 210 ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 6

... V + 0.5 V – -40°C to 85° Minimum Typical Maximum V – 1.4 V – 0.9 CCO CCO V – 2.0 V – 1.7 CCO CCO 0.6 1.0 ICS843002AKI-40 REV. B APRIL 27, 2009 = 0V, Units V V µA µA µA µ Units µA µA µ Units ...

Page 7

... EE A Minimum Typical Maximum V – 1.4 V CCO CCO V – 2.0 V CCO CCO 0.4 1.0 = 3.3V±5% or 2.5V±5 Minimum Typical Maximum 19.44 0.81 100 45 ICS843002AKI-40 REV. B APRIL 27, 2009 Units – 0.9 V – 1 0V, Units 175 MHz 150 ps ps 800 ...

Page 8

... Typical Phase Noise at 155.52MHz Phase Noise Result by adding a filter to raw data IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Filter Raw Phase Noise Data Offset Frequency (Hz) 8 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical) ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 9

... CCO_LVPECL nQx -0.5V ± 0.125V 3.3V Core/2.5V LVPECL Output Load AC Test Circuit nQx Qx V nQy CMR Qy Output Skew nQA, nQB Phase Noise Mask QA Output Rise/Fall Time 9 2V 2.8V ± 0.04V V CCA LVPECL V EE tsk(o) 80% 80% 20 ICS843002AKI-40 REV. B APRIL 27, 2009 SCOPE Qx nQx 20 ...

Page 10

... All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. 10 ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 11

... IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR CC, should be individually requires that CCA / Figure 2. Single-Ended Signal Driving Differential Input 11 3. .01µF 10Ω V CCA .01µF 10µF Figure 1. Power Supply Filtering Single Ended Clock Input CLKx V_REF nCLKx C1 0. ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 12

... Zo = 50Ω R1 100 Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS843002AKI-40 REV. B APRIL 27, 2009 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...

Page 13

... These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. SOLDER EXPOSED HEAT SLUG LAND PATTERN (GROUND PAD) THERMAL VIA 13 PIN PIN PAD ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 14

... Input R2 50Ω RTT Figure 5B. 3.3V LVPECL Output Termination 14 3. 125Ω 125Ω 50Ω LVPECL Z = 50Ω 84Ω 84Ω ICS843002AKI-40 REV. B APRIL 27, 2009 3.3V Input ...

Page 15

... The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. – very close to CCO 2.5V 2.5V R3 250 + – 62.5 62.5 Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V + – 2.5V CC 50Ω 50Ω 2.5V LVPECL Driver R1 50 ICS843002AKI-40 REV. B APRIL 27, 2009 2.5V + – ...

Page 16

... The LOR output will otherwise be low phase detector observation interval, the activity monitor does not flag excessive reference transitions as an error. The monitor only distinguishes between transitions occurring and no transitions occurring. 16 ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 17

... LF0 LF1 ISET SET XTAL_IN C TUNE 19.44MHz XTAL_OUT C TUNE Ω C (µ SET 0.10 9.5 0.01 4.75 0.01 4.75 Minimum Typical Maximum Fundamental 19.44 ±20 ±20 -40 + 220 240 50 1 ±3 per year ICS843002AKI-40 REV. B APRIL 27, 2009 , Units MHz ppm ppm Ω mW ppm ...

Page 18

... IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR = 3. 3.465V, which gives worst case results 3.465V * 210mA = 727.65mW EE_MAX * Pd_total + for 48 Lead TQFP, Forced Convection θ by Velocity JA 0 37.0°C/W 18 must be used. Assuming no air flow JA 1 2.5 32.4°C/W 29.0°C/W ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 19

... IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR V OUT RL 50Ω CCO = V – 0.9V CCO_MAX = V – 1.7V CCO_MAX ] * (V – [(2V – CCO_MAX OH_MAX ] * (V – [(2V – CCO_MAX OL_MAX 19 – V ))/ CCO_MAX OH_MAX L CCO_MAX – V ))/ CCO_MAX OL_MAX L] CCO_MAX ICS843002AKI-40 REV. B APRIL 27, 2009 – OH_MAX – OL_MAX ...

Page 20

... Air Flow Table for a 32 Lead VFQFN JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS843002I-40 is: 5536 IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR θ vs. Air Flow 37.0°C/W 32.4°C/W 20 2.5 29.0°C/W ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 21

... Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR -1 ef Anvil Singula tion (Ref.) N & N Odd Maximum 1.00 0.05 0.30 8 3.3 0.50 21 (Ref.) N & N Even N e (Ty p & are Even 2 (N -1)x e (Re f mal ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 22

... Lead VFQFN 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN 22 Shipping Packaging Temperature Tray -40°C to 85°C 2500 Tape & Reel -40°C to 85°C Tray -40°C to 85°C 2500 Tape & Reel -40°C to 85°C ICS843002AKI-40 REV. B APRIL 27, 2009 ...

Page 23

... Revision History Sheet Rev Table Page Description of Change A T4B 6 LVCMOS DC Characteristics Table - added conditions Characteristics Table - changed output skew from 50ps max. to 150ps max. IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR and ICS843002AKI-40 REV. B APRIL 27, 2009 Date . 1/22/09 4/27/09 ...

Page 24

ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the ...

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