ICS843002AKI-40LF IDT, Integrated Device Technology Inc, ICS843002AKI-40LF Datasheet - Page 14

• Manufacturer Part Number: ICS843002AKI-40LF
• Description: IC SYNTHESIZER LVPECL 32-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™, FemtoClock®r
• Type: Clock Generator, Clock Synchronizer, Frequency Translator, Jitter Attenuator, Multiplexerr

Specifications of ICS843002AKI-40LF

• Pll: Yes with Bypass
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTLL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 175MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN
• Frequency-max: 175MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 843002AKI-40LF

Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential output is a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 5A. 3.3V LVPECL Output Termination
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
ICS843002I-40
175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
14
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 5B. 3.3V LVPECL Output Termination
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
ICS843002AKI-40 REV. B APRIL 27, 2009
R3
125Ω
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input