ICS843002AKI-40LF IDT, Integrated Device Technology Inc, ICS843002AKI-40LF Datasheet - Page 11

• Manufacturer Part Number: ICS843002AKI-40LF
• Description: IC SYNTHESIZER LVPECL 32-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™, FemtoClock®r
• Type: Clock Generator, Clock Synchronizer, Frequency Translator, Jitter Attenuator, Multiplexerr

Specifications of ICS843002AKI-40LF

• Pll: Yes with Bypass
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTLL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 175MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN
• Frequency-max: 175MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 843002AKI-40LF

Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The
ICS843002I-40 provides separate power supplies to isolate any
high switching noise from the outputs to the internal PLL. V
V
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
an additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the V
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
CCA,
ICS843002I-40
175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
V
CCO_LVPECL
CC
CCA
and V
pin and also shows that V
pin.
CC
CCO_LVCMOS
= 3.3V, V_REF should be 1.25V and
should be individually
CCA
requires that
CC
/2 is
CC,
11
Figure 2. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
Figure 1. Power Supply Filtering
V
C1
0.1u
V
CCA
V_REF
CC
ICS843002AKI-40 REV. B APRIL 27, 2009
.01µF
.01µF
R1
1K
R2
1K
3.3V
V
CC
10Ω
10µF
CLKx
nCLKx