IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet
IDT82V3255TFG
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WAN PLL IDT82V3255 Version 5 December 3, 2008 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. © 2008 Integrated Device Technology, Inc. ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 13 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 17 3.1 RESET ........................................................................................................................................................................................................... ...
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IDT82V3255 3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31 3.10.1.5 Holdover Mode ................................................................................................................................................................. 31 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32 3.10.1.5.4 Manual ........................................................................................................................................................... 32 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32 3.10.1.6 ...
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IDT82V3255 8.3.2.1 PECL Input / Output Port ................................................................................................................................................ 114 8.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 116 8.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 117 8.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 120 8.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 121 8.7 OUTPUT ...
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Table 1: Pin Description ............................................................................................................................................................................................. 13 Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 17 Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18 Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 19 Table ...
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IDT82V3255 Table 49: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 118 Table 50: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 118 Table 51: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 119 Table 52: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... ...
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Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 19 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 20 Figure 5. External Fast Selection ................................................................................................................................................................................ 22 Figure ...
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FEATURES HIGHLIGHTS • The first single PLL chip: • Features 0 560 Hz bandwidth • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM and ...
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IDT82V3255 DESCRIPTION The IDT82V3255 is an integrated, single-chip solution for the Syn- chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, ...
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IDT82V3255 FUNCTIONAL BLOCK DIAGRAM Functional Block Diagram Figure 1. Functional Block Diagram 11 WAN PLL December 3, 2008 ...
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IDT82V3255 1 PIN ASSIGNMENT AGND IC1 AGND1 VDDA1 INT_REQ OSCI DGND1 VDDD1 VDDD3 DGND3 DGND2 VDDD2 FF_SRCSW VDDA2 AGND2 IC2 Pin Assignment IDT82V3255 Figure ...
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IDT82V3255 2 PIN DESCRIPTION Table 1: Pin Description Name Pin No. OSCI 6 FF_SRCSW 13 SONET/SDH 64 48 RST EX_SYNC1 28 EX_SYNC2 33 EX_SYNC3 35 IN1_CMOS 29 IN2_CMOS 30 IN1_POS 23 IN1_NEG 24 IN2_POS 25 IN2_NEG 26 Pin Description I/O ...
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IDT82V3255 Table 1: Pin Description (Continued) Name Pin No. IN3_CMOS 34 FRSYNC_8K 17 MFRSYNC_2K 18 OUT1_POS 19 OUT1_NEG 20 OUT2 INT_REQ 5 SDI 43 CLKE 42 SDO 52 SCLK 47 TRST 37 TMS 41 Pin Description I/O ...
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IDT82V3255 Table 1: Pin Description (Continued) Name Pin No. TCK 49 TDI 51 TDO 50 VDDD1 8 VDDD2 12 VDDD3 9 VDDD4 32 VDDD5 36, 38, 39, 45, 46 VDDD6 54 VDDA1 4 VDDA2 14 VDDA3 57 VDD_DIFF 22 DGND1 ...
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IDT82V3255 Table 1: Pin Description (Continued) Name Pin No. IC1 2 IC2 16 IC3 55 IC4 59 IC5 60 IC6 61 IC7 62 IC8 Note: 1. All the unused input pins should be connected to ground; the ...
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IDT82V3255 3 FUNCTIONAL DESCRIPTION 3.1 RESET The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must ...
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IDT82V3255 3.3 INPUT CLOCKS & FRAME SYNC SIGNALS Altogether 5 clocks and 3 frame sync signals are input to the device. 3.3.1 INPUT CLOCKS The device provides 5 input clock ports. According to the input port technology, the input ports ...
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IDT82V3255 3.4 INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the DPLL required fre- quency, which is no more than 38.88 MHz. For each input clock, ...
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IDT82V3255 3.5 INPUT CLOCK QUALITY MONITORING The qualities of all the input clocks are always monitored in the fol- lowing aspects: • Activity • Frequency The qualified clocks are available for T0/T4 DPLL selection. The T0 and T4 selected input ...
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IDT82V3255 3.5.2 FREQUENCY MONITORING Frequency is monitored by comparing the input clock with a refer- ence clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A ...
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IDT82V3255 3 DPLL INPUT CLOCK SELECTION An input clock is selected for T0 DPLL and for T4 DPLL respectively. For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter- mine the input clock selection, as shown ...
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IDT82V3255 3.6.2 FORCED SELECTION In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni- toring) do not affect the input ...
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IDT82V3255 3.7 SELECTED INPUT CLOCK MONITORING The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7 DPLL LOCKING DETECTION The ...
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IDT82V3255 3.7.3 PHASE LOCK ALARM (T0 ONLY) A phase lock alarm will be raised when the selected input clock can not be locked in T0 DPLL within a certain period. This period can be cal- culated as follows: Period (sec.) ...
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IDT82V3255 3.8 SELECTED INPUT CLOCK SWITCH If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection (T0 only) Selection) any ...
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IDT82V3255 3.8.2.2 Non-Revertive Switch (T0 only) In Non-Revertive switch, the T0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. In this case, the selected input ...
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IDT82V3255 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE The operating modes supported by T0 DPLL are more complex than the ones supported by T4 DPLL for T0 path is the main one. T0 DPLL supports three primary operating ...
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IDT82V3255 15 Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode Notes to Figure 6: 1. Reset input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. ...
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IDT82V3255 The causes of Item ‘the T0 selected input clock is switched to another one’ - are: (The T0 selected input clock is disquali- fied AND Another input clock is switched to) OR (In Revertive ...
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IDT82V3255 3. DPLL OPERATING MODE The T0/T4 DPLL gives a stable performance in different applications without being affected by operating conditions or silicon process varia- tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low ...
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IDT82V3255 phase locked to any input clock. The frequency offset acquiring method is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 20: Table 20: Frequency Offset Control in Holdover Mode MAN_HOLDOVER AUTO_AVG ...
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IDT82V3255 phase locked to any input clock. The T4 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10 ppm. Table 22: Related Bit / Register in Chapter 3.10 Bit CURRENT_PH_DATA[15:0] CURRENT_DPLL_FREQ[23:0] T0_DPLL_START_BW[4:0] T0_DPLL_START_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] ...
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IDT82V3255 3. DPLL OUTPUT The DPLL output is locked to the selected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is ...
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IDT82V3255 3.11.5.2 T4 Path The four paths for T4 DPLL output are as follows: • 77.76 MHz path - outputs a 77.76 MHz clock; • 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit; ...
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IDT82V3255 3. APLL A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] ...
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IDT82V3255 Table 26: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL OUTn_DIVIDER[3:0] 1 (Output Divider) 77.76 MHz X 4 12E1 X 4 0000 3 0001 622.08 MHz 3 0010 48E1 311.04 MHz 0011 155.52 MHz 24E1 0100 77.76 ...
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IDT82V3255 3.13.2 FRAME SYNC OUTPUT SIGNALS An 8 kHz and a 2 kHz frame sync signals are output on the FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and 2K_EN bits respectively. They are CMOS outputs. The two frame ...
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IDT82V3255 T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks Figure 10. 0.5 UI Late Frame Sync Input Signal Timing Table 29: Related Bit / Register in Chapter 3.13 Bit OUT1_PECL_LVDS OUTn_PATH_SEL[3: ...
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IDT82V3255 3.14 INTERRUPT SUMMARY The interrupt sources of the device are as follows: • T4 DPLL locking status change • Input clocks for T0 path validity change • T0 selected input clock fail • Input clocks for T4 path change ...
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IDT82V3255 3.16 POWER SUPPLY FILTERING TECHNIQUES 3. 3V SLF7028T-100M1R1 3.3V SLF7028T-100M1R1 0.1 µF 0.1 µF 10 µF To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources of ...
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IDT82V3255 3.17 LINE CARD APPLICATION Master Clock Board Slave Clock Board Standby Clock Board Functional Description OC-N Clock Sync Clock Clock Sync IDT82V3255 Clock Sync Sync OC-n Line Card Board Backplane Figure 13. Line Card Application 42 SDH/SONET System Optical ...
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IDT82V3255 4 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The microprocessor interface supports Serial mode only read operation, the active edge of SCLK is selected by CLKE. When CLKE ...
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IDT82V3255 Table 31: Read Timing Characteristics in Serial Mode Symbol T One cycle time of the master clock out t Valid SDI to valid SCLK setup time su1 t Valid CS to valid SCLK setup time su2 ...
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IDT82V3255 5 JTAG This device is compliant with the IEEE 1149.1 Boundary Scan stan- dard except the following: • The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; • ...
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IDT82V3255 6 PROGRAMMING INFORMATION After reset, all the registers are set to their default values. The regis- ters are read or written via the microprocessor interface. Before any write operation, PROTECTION_CNFG is recommended to be confirmed to make sure whether ...
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IDT82V3255 Table 34: Register List and Map (Continued) Address Register Name (Hex) MON_SW_PBO_CNFG - Frequency 0B Monitor, Input Clock Selection & PBO Control PROTECTION_CNFG - Register Pro- 7E tection Mode Configuration INTERRUPT_CNFG - Interrupt Config- 0C uration INTERRUPTS1_STS - Interrupt ...
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IDT82V3255 Table 34: Register List and Map (Continued) Address Register Name (Hex) IN3_CMOS_SEL_PRIORITY_CNFG - 2A CMOS Input Clock 3 Priority Configu- ration * FREQ_MON_FACTOR_CNFG - Fac- 2E tor of Frequency Monitor Configuration ALL_FREQ_MON_THRESHOLD_CN Frequency Monitor Threshold for ...
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IDT82V3255 Table 34: Register List and Map (Continued) Address Register Name (Hex) IN_FREQ_READ_CH_CNFG - Input 41 Clock Frequency Read Channel Selection IN_FREQ_READ_STS - Input Clock 42 Frequency Read Value IN1_IN2_CMOS_STS - CMOS Input 44 Clock 1 & 2 Status IN1_IN2_DIFF_STS ...
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IDT82V3255 Table 34: Register List and Map (Continued) Address Register Name (Hex) T0_BW_OVERSHOOT_CNFG - T0 59 DPLL Bandwidth Overshoot Configu- ration PHASE_LOSS_COARSE_LIMIT_CNF Phase Loss Coarse Detector Limit Configuration * PHASE_LOSS_FINE_LIMIT_CNFG - 5B Phase Loss Fine Detector Limit ...
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IDT82V3255 Table 34: Register List and Map (Continued) Address Register Name (Hex) OUT2_INV_CNFG - Output Clock 2 73 Invert Configuration FR_MFR_SYNC_CNFG - Frame Sync 74 & Multiframe Sync Output Configura- tion PHASE_MON_PBO_CNFG - Phase 78 Transient Monitor & PBO Configura- ...
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IDT82V3255 NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 Address: 04H Type: Read / Write Default Value: 00000000 7 6 NOMINAL_FRE NOMINAL_FRE Q_VALUE7 Q_VALUE6 Bit Name NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, ...
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IDT82V3255 T4_T0_REG_SEL_CNFG - Registers Selection Configuration Address: 07H Type: Read / Write Default Value: XXX0XXXX Bit Name Reserved. A part of the registers are shared by T0 and T4 ...
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IDT82V3255 INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100X10 7 6 AUTO_EXT_SY EXT_SYNC_EN NC_EN Bit Name This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’. 7 AUTO_EXT_SYNC_EN Refer to the ...
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IDT82V3255 DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX00X Bit Name Reserved. This bit selects a better active edge of ...
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IDT82V3255 MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 6 FREQ_MON_C LOS_FLAG_TO ULTR_FAST_SW LK _TDO Bit Name The bit selects a reference clock for input clock frequency monitoring. ...
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IDT82V3255 PROTECTION_CNFG - Register Protection Mode Configuration Address: 7EH Type: Read / Write Default Value: 10000101 7 6 PROTECTION_ PROTECTION_ PROTECTION_ DATA7 DATA6 Bit Name PROTECTION_DATA[7:0] Programming Information 5 4 PROTECTION_ PROTECTION_ DATA5 DATA4 These bits select ...
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IDT82V3255 6.2.2 INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 Bit Name Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The ...
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IDT82V3255 INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00XXXXX1 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED IN3_CMOS Programming Information This ...
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IDT82V3255 INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read / Write Default Value: 11X1XXXX 7 6 EX_SYNC_ALARM T4_STS Bit Name This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ...
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IDT82V3255 INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2 Address: 11H Type: Read / Write Default Value:00XXXXX0 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED IN3_CMOS INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: ...
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IDT82V3255 6.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CMOS_CNFG - CMOS Input Clock 1 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the ...
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IDT82V3255 IN2_CMOS_CNFG - CMOS Input Clock 2 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the ...
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IDT82V3255 IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 7 6 IN2_DIFF_DIV1 IN2_DIFF_DIV0 Bit Name These bits determine whether the HF Divider is used and what the ...
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IDT82V3255 IN1_DIFF_CNFG - Differential Input Clock 1 Configuration Address: 19H Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 19H). This bit, together with ...
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IDT82V3255 IN2_DIFF_CNFG - Differential Input Clock 2 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1AH). This bit, together with ...
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IDT82V3255 IN3_CMOS_CNFG - CMOS Input Clock 3 Configuration Address: 1DH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1DH). This bit, together with ...
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IDT82V3255 PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 Bit Name PRE_DIV_CH_VALUE[3:0] PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 ...
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IDT82V3255 PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 6 PRE_DIVN_VAL PRE_DIVN_VAL - UE14 Bit Name PRE_DIVN_VALUE[14:8] Programming Information 5 4 PRE_DIVN_VAL PRE_DIVN_VAL UE13 UE12 ...
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IDT82V3255 IN1_IN2_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 1 & 2 Priority Configuration * Address: 27H Type: Read / Write Default Value: 00110010 7 6 IN2_CMOS_SE IN2_CMOS_SE IN2_CMOS_SE L_PRIORITY3 L_PRIORITY2 L_PRIORITY1 Bit Name INn_CMOS_SEL_PRIORITY[3: INn_CMOS_SEL_PRIORITY[3:0] Programming ...
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IDT82V3255 IN1_IN2_DIFF_SEL_PRIORITY_CNFG - Differential Input Clock 1 & 2 Priority Configuration * Address: 28H Type: Read / Write Default Value: 00000000 7 6 IN2_DIFF_SEL_ IN2_DIFF_SEL_ IN2_DIFF_SEL_ PRIORITY3 PRIORITY2 Bit Name INn_DIFF_SEL_PRIORITY[3: INn_DIFF_SEL_PRIORITY[3:0] Programming Information ...
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IDT82V3255 IN3_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 3 Priority Configuration * Address: 2AH Type: Read / Write Default Value: XXXX0100 Bit Name IN3_CMOS_SEL_PRIORITY[3:0] Programming Information IN3_CMOS_SE - ...
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IDT82V3255 6.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 Bit Name FREQ_MON_FACTOR[3:0] ...
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IDT82V3255 UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE SHOLD_0_DAT SHOLD_0_DAT A7 A6 Bit Name UPPER_THRESHOLD_0_DATA[7:0] LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket ...
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IDT82V3255 DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_0_DATA[1:0] UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket ...
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IDT82V3255 BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 6 BUCKET_SIZE BUCKET_SIZE BUCKET_SIZE _1_DATA7 _1_DATA6 Bit Name BUCKET_SIZE_1_DATA[7:0] DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration ...
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IDT82V3255 LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 6 LOWER_THRE LOWER_THRE LOWER_THRE SHOLD_2_DAT SHOLD_2_DAT SHOLD_2_DAT A7 A6 Bit Name LOWER_THRESHOLD_2_DATA[7:0] BUCKET_SIZE_2_CNFG - Bucket Size for ...
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IDT82V3255 UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE UPPER_THRE SHOLD_3_DAT SHOLD_3_DAT SHOLD_3_DAT A7 A6 Bit Name UPPER_THRESHOLD_3_DATA[7:0] LOWER_THRESHOLD_3_CNFG - Lower Threshold for ...
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IDT82V3255 DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_3_DATA[1:0] IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel ...
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IDT82V3255 IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 7 6 IN_FREQ_VAL IN_FREQ_VAL UE7 UE6 Bit Name These bits represent a 2’s complement signed integer. If the value is multiplied by the value in ...
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IDT82V3255 IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status Address: 44H Type: Read Default Value: X110X110 7 6 IN2_CMOS_FRE IN2_CMOS_NO_ - Q_HARD_ALAR ACTIVITY_ALAR M Bit Name IN2_CMOS_FREQ_HARD_ALARM 5 IN2_CMOS_NO_ACTIVITY_ALARM 4 IN2_CMOS_PH_LOCK_ALARM IN1_CMOS_FREQ_HARD_ALARM 1 ...
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IDT82V3255 IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status Address: 45H Type: Read Default Value: X110X110 7 6 IN2_DIFF_FREQ IN2_DIFF_NO_A - _HARD_ALARM CTIVITY_ALARM Bit Name IN2_DIFF_FREQ_HARD_ALARM 5 IN2_DIFF_NO_ACTIVITY_ALARM 4 IN2_DIFF_PH_LOCK_ALARM IN1_DIFF_FREQ_HARD_ALARM 1 IN1_DIFF_NO_ACTIVITY_ALARM ...
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IDT82V3255 IN3_CMOS_STS - CMOS Input Clock 3 Status Address: 47H Type: Read Default Value: XXXXX110 Bit Name IN3_CMOS_FREQ_HARD_ALARM 1 IN3_CMOS_NO_ACTIVITY_ALARM 0 IN3_CMOS_PH_LOCK_ALARM Programming Information Reserved. ...
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IDT82V3255 6.2 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: XX0000XX Bit Name Reserved. This bit indicates the validity of ...
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IDT82V3255 PRIORITY_TABLE1_STS - Priority Status 1 * Address: 4EH Type: Read Default Value: 00000000 7 6 HIGHEST_PRI HIGHEST_PRI ORITY_VALIDA ORITY_VALIDA ORITY_VALIDA TED3 TED2 Bit Name HIGHEST_PRIORITY_VALIDATED[3: CURRENTLY_SELECTED_INPUT[3:0] Programming Information 5 4 HIGHEST_PRI HIGHEST_PRI CURRENTLY_S ...
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IDT82V3255 PRIORITY_TABLE2_STS - Priority Status 2 * Address: 4FH Type: Read Default Value: 00000000 7 6 THIRD_HIGHE THIRD_HIGHE THIRD_HIGHE ST_PRIORITY_ ST_PRIORITY_ ST_PRIORITY_ VALIDATED3 VALIDATED2 Bit Name THIRD_HIGHEST_PRIORITY_VALIDATED[3: SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] T0_INPUT_SEL_CNFG - T0 Selected Input Clock ...
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IDT82V3255 T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration Address: 51H Type: Read / Write Default Value: X0000000 T4_LOCK_T0 T0_FOR_T4 Bit Name 7 - Reserved. This bit determines whether the T4 DPLL locks DPLL output ...
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IDT82V3255 6.2 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 7 6 EX_SYNC_ALA T4_DPLL_LO T0_DPLL_SOFT RM_MON CK _FREQ_ALARM Bit Name 7 EX_SYNC_ALARM_MON 6 T4_DPLL_LOCK 5 T0_DPLL_SOFT_FREQ_ALARM 4 T4_DPLL_SOFT_FREQ_ALARM ...
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IDT82V3255 T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 Bit Name T0_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration ...
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IDT82V3255 6.2 DPLL & APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 6 T0_APLL_PATH T0_APLL_PA T0_APLL_PA 3 TH2 Bit Name T0_APLL_PATH[3:0] ...
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IDT82V3255 T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_STA T0_DPLL_STA T0_DPLL_STA RT_DAMPING2 RT_DAMPING1 RT_DAMPING0 Bit Name T0_DPLL_START_DAMPING[2: T0_DPLL_START_BW[4:0] Programming Information ...
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IDT82V3255 T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_ACQ T0_DPLL_ACQ T0_DPLL_ACQ _DAMPING2 _DAMPING1 Bit Name T0_DPLL_ACQ_DAMPING[2: T0_DPLL_ACQ_BW[4:0] Programming Information 5 ...
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IDT82V3255 T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_LOCK T0_DPLL_LOCK T0_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 Bit Name T0_DPLL_LOCKED_DAMPING[2: T0_DPLL_LOCKED_BW[4:0] T0_BW_OVERSHOOT_CNFG - T0 ...
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IDT82V3255 PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 7 6 COARSE_PH_L WIDE_EN MULTI_PH_APP OS_LIMT_EN Bit Name This bit controls whether the occurrence of the coarse phase loss will result ...
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IDT82V3255 PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 7 6 FINE_PH_LOS_ FAST_LOS_SW LIMT_EN Bit Name 7 FINE_PH_LOS_LIMT_EN 6 FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] Programming Information ...
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IDT82V3255 T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 6 MAN_HOLDOV AUTO_AVG ER Bit Name 7 MAN_HOLDOVER 6 AUTO_AVG 5 FAST_AVG 4 READ_AVG TEMP_HOLDOVER_MODE[1: ...
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IDT82V3255 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 6 T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER _FREQ15 _FREQ14 Bit Name T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, ...
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IDT82V3255 T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration Address: 60H Type: Read / Write Default Value: 01000X0X 7 6 T4_APLL_PATH T4_APLL_PA T4_APLL_PA 3 TH2 Bit Name T4_APLL_PATH[3: T4_GSM_GPS_16E1_16T1_SEL[1: T4_12E1_24T1_E3_T3_SEL[1:0] Programming ...
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IDT82V3255 T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration Address: 61H Type: Read / Write Default Value: 011XXX00 7 6 T4_DPLL_LOCK T4_DPLL_LOCK T4_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 ED_DAMPING0 Bit Name T4_DPLL_LOCKED_DAMPING[2: ...
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IDT82V3255 CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 64H Type: Read Default Value: 00000000 7 6 CURRENT_DP CURRENT_DP CURRENT_DP LL_FREQ23 LL_FREQ22 Bit Name CURRENT_DPLL_FREQ[23:16] DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / ...
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IDT82V3255 DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 67H Type: Read / Write Default Value: 00011001 7 6 DPLL_FREQ_H DPLL_FREQ_H ARD_LIMT15 ARD_LIMT14 Bit Name DPLL_FREQ_HARD_LIMT[15:8] CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * Address: 68H Type: ...
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IDT82V3255 T0_T4_APLL_BW_CNFG - APLL Bandwidth Configuration Address: 6AH Type: Read / Write Default Value: XX01XX01 T0_APLL_BW1 Bit Name Reserved. These bits set the bandwidth for T0 APLL. 00: 100 ...
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IDT82V3255 6.2.8 OUTPUT CONFIGURATION REGISTERS OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 6 OUT2_PATH_S OUT2_PATH_S OUT2_PATH_S EL3 EL2 Bit Name These bits select an input to OUT2. 0000 ~ 0011: ...
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IDT82V3255 OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address:71H Type: Read / Write Default Value: 00001000 7 6 OUT1_PATH_S OUT1_PATH_S OUT1_PATH_S EL3 EL2 Bit Name These bits select an input to OUT1. 0000 ~ 0011: The output of T0 APLL. ...
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IDT82V3255 OUT2_INV_CNFG - Output Clock 2 Invert Configuration Address:73H Type: Read / Write Default Value: XXXXX0XX Bit Name Reserved. This bit determines whether the output on OUT2 is inverted. 2 OUT2_INV 0: ...
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IDT82V3255 FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 7 6 IN_2K_4K_8K_I 8K_EN NV Bit Name 7 IN_2K_4K_8K_INV 6 8K_EN 5 2K_EN 4 2K_8K_PUL_POSITION 3 8K_INV 2 8K_PUL 1 2K_INV 0 ...
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IDT82V3255 6.2.9 PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 6 IN_NOISE_WIN - DOW Bit Name 7 IN_NOISE_WINDOW PH_MON_EN 4 PH_MON_PBO_EN 3 ...
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IDT82V3255 PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 7 6 PH_OFFSET_E - N Bit Name This bit determines whether the input-to-output phase offset is enabled. 7 PH_OFFSET_EN 0: Disabled. (default) 1: Enabled. 6 ...
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IDT82V3255 6.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: 00101011 7 6 SYNC_BYPASS SYNC_MON_LIMT2 Bit Name This bit selects one frame sync input signal to synchronize the frame sync output signals. 0: ...
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IDT82V3255 SYNC_PHASE_CNFG - Sync Phase Configuration Address:7DH Type: Read / Write Default Value: XX000000 Bit Name Reserved. These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame ...
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IDT82V3255 7 THERMAL MANAGEMENT The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T should not exceed 125°C. In some jmax applications, the device ...
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IDT82V3255 8 ELECTRICAL SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATING Table 37: Absolute Maximum Rating Symbol OUT T Ambient Operating Temperature Range A T STOR 8.2 RECOMMENDED OPERATION CONDITIONS Table 38: Recommended Operation Conditions Symbol Parameter V ...
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IDT82V3255 8.3 I/O SPECIFICATIONS 8.3.1 CMOS INPUT / OUTPUT PORT From Table 39 to Table 42 3 Table 39: CMOS Input Port Electrical Characteristics Parameter Description V Input Voltage High IH V Input Voltage Low IL ...
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IDT82V3255 8.3.2 PECL / LVDS INPUT / OUTPUT PORT 8.3.2.1 PECL Input / Output Port 130 Ω 50 Ω (transmission line) 82 Ω 2 kHz to 667 MHz 130 Ω ...
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IDT82V3255 Table 43: PECL Input / Output Port Electrical Characteristics Parameter Description V Input Low Voltage, Differential Inputs IL V Input High Voltage, Differential Inputs IH V Input Differential Voltage ID V Input Low Voltage, Single-ended Input IL_S V Input ...
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IDT82V3255 8.3.2.2 LVDS Input / Output Port 50 Ω (transmission line) 2 kHz to 100 Ω 667 MHz 50 Ω (transmission line) 50 Ω (transmission line) 2 kHz to 100 Ω 667 MHz 50 Ω (transmission line) Figure 20. Recommended ...
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IDT82V3255 8.4 JITTER & WANDER PERFORMANCE Table 45: Output Clock Jitter Generation 1 Test Definition N x 2.048MHz without APLL N x 2.048MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44.736 ...
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IDT82V3255 Table 46: Output Clock Phase Noise 1 Output Clock 622.08 MHz (T0 DPLL + T0/T4 APLL) 155.52 MHz (T0 DPLL + T0/T4 APLL) 38.88 MHz (T0 DPLL + T0/T4 APLL) 16E1 (T0/T4 APLL) 16T1 (T0/T4 APLL) E3 (T0/T4 APLL) ...
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IDT82V3255 Table 51: T0 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor 0.1 Hz 0.3 Hz 0.6 Hz 1 560 Hz Electrical Specifications ...
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IDT82V3255 8.5 OUTPUT WANDER GENERATION template tested result Electrical Specifications Figure 22. Output Wander Generation 120 WAN PLL template tested result December 3, 2008 ...
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IDT82V3255 8.6 INPUT / OUTPUT CLOCK TIMING The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. 8 kHz Input Clock 8 kHz Output Clock 6.48 MHz Input Clock ...
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IDT82V3255 8.7 OUTPUT CLOCK TIMING Table 54: Output Clock Timing Symbol Electrical Specifications MFRSYNC_2K/ ...
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ADSL --- AMI --- APLL --- ATM --- BITS --- CMOS --- DCO --- DPLL --- DSL --- DSLAM --- DWDM --- EPROM --- GPS --- GSM --- IIR --- IP --- ISDN --- JTAG --- LOS --- ...
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IDT82V3255 PBO --- PDH --- PECL --- PFD --- PLL --- RMS --- PRS --- SDH --- SEC --- SMC --- SONET --- SSU --- STM --- TCM-ISDN --- TDEV --- --- UI WLL --- Glossary Phase Build-Out Plesiochronous Digital ...
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A Averaged Phase Error ........................................................................ 31 B Bandwidths and Damping Factors ..................................................... 31 Acquisition Bandwidth and Damping Factor ............................... 31 Locked Bandwidth and Damping Factor ..................................... 31 Starting Bandwidth and Damping Factor .................................... 31 C Calibration .......................................................................................... 17 Coarse Phase ...
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IDT82V3255 HF Divider ................................................................................... 19 Lock 8k Divider ........................................................................... 19 R Reference Clock ................................................................................. 21 S Selected Input Clock Switch ............................................................... 26 Index Non-Revertive switch ................................................................. 27 Revertive switch ......................................................................... 26 State Machine ..............................................................................28 V Validity ............................................................................................... 26 126 WAN ...
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IDT82V3255 PACKAGE DIMENSIONS Figure 24. 64-Pin PP Package Dimensions (a) (in Millimeters) Package Dimensions 127 WAN PLL December 3, 2008 ...
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IDT82V3255 Figure 25. 64-Pin PP Package Dimensions (b) (in Millimeters) Package Dimensions 128 WAN PLL December 3, 2008 ...
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IDT82V3255 Figure 26. 64-Pin EDG Package Dimensions (a) (in Millimeters) Package Dimensions 129 WAN PLL December 3, 2008 ...
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IDT82V3255 Figure 27. 64-Pin EDG Package Dimensions (b) (in Millimeters) Package Dimensions 130 WAN PLL December 3, 2008 ...
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IDT82V3255 Figure 28. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters) Package Dimensions 131 WAN PLL December 3, 2008 ...
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IDT82V3255 ORDERING INFORMATION XXXXXXX XX Device Type DATASHEET DOCUMENT HISTORY 09/28/2005 pgs. 112. 06/19/2006 pgs. 41 03/14/2007 pgs. 111 11/18/2008 pgs. 111, 112, 117, 127, 128, 129, 130, 131, 132 12/03/2008 pg. 132 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road ...