IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 15

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

Table 1: Pin Description (Continued)
Pin Description
IDT82V3255
GND_DIFF
VDD_DIFF
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
AGND1
AGND2
AGND3
VDDA1
VDDA2
VDDA3
AGND
Name
TCK
TDO
TDI
36, 38, 39, 45, 46
Pin No.
49
51
50
12
32
54
14
57
22
11
10
31
40
53
15
58
21
8
9
4
7
3
1
pull-down
Ground
Ground
Ground
Ground
pull-up
Power
Power
Power
I/O
O
I
I
CMOS
CMOS
CMOS
Type
-
-
-
-
-
-
-
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.
VDDAn: 3.3 V Analog Power Supply
Each VDDAn should be paralleled with ground through a 0.1 µF capacitor.
VDD_DIFF: 3.3 V Power Supply for OUT1
DGNDn: Digital Ground
AGNDn: Analog Ground
GND_DIFF: Ground for OUT1
AGND: Analog Ground
Power & Ground
15
Description
Chapter 3.8.1 Input Clock Validity
1
December 3, 2008
for details.
WAN PLL