DS1073M-100 Maxim Integrated Products, DS1073M-100 Datasheet - Page 6

• Manufacturer Part Number: DS1073M-100
• Description: ECONOSCILLATOR/DIV 100MHZ 8-DIP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1073M-100

• Frequency: 100MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

OPERATION OF OUTPUT ENABLE
Since the output enable, internal master oscillator and/or external master oscillator are likely all
asynchronous there is the possibility of timing difficulties in the application.
difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is
enabled and disabled. In particular the output gating is configured so that truncated output pulses can
never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the prescaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (t
of MCLK. If the actual setup time is less than t
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE.
Figure 4
DISABLE TIMING
If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If
OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE
and the rising edge of MCLK. If t
output before disabling occurs.
If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if t
one additional output pulse will appear, if t
The following diagrams illustrate the timing in each of these cases.
Figure 5
SU
< t
SUEM
SU
< t
the result will be one additional pulse appearing on the
SUEM
SU
6 of 18
SUEM,
) from a transition on the OE input to the rising edge
then two additional output pulses will appear.
then one more complete cycle of MCLK will be
t
t
t
MAX VALUE OF t
MIN VALUE OF t
M
d
OUTH
= PROP DELAY FROM MCLK ­ TO OUT ­
= PERIOD OF MCLK
t
t
MAX VALUE OF t
MIN VALUE OF ten = t
M
d
= PROP DELAY FROM MCLK ­ TO OUT ­
= WIDTH OF OUTPUT PULSE
= PERIOD OF MCLK
dis
dis
= 0
= t
en
SUEM
= t
SUEM
SUEM
+ t
To minimize these
d
+ t
+ 2 t
+ t
M
OUTH
M
+ t
+ t
d
SU
d
> t
SUEM