DS1073M-100 Maxim Integrated Products, DS1073M-100 Datasheet - Page 8

• Manufacturer Part Number: DS1073M-100
• Description: ECONOSCILLATOR/DIV 100MHZ 8-DIP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1073M-100

• Frequency: 100MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

FROM EXTERNAL TO INTERNAL CLOCK
This is accomplished by a low to high transition on the
triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if
a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal
reference. (Level triggering was not employed for the switch from internal to external reference as this
approach is slower and the internal clock may be running at a much higher frequency than the maximum
allowed external clock rate). When
held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed
through to OUT0.
Figure 8
Depending on the relative timing of the
t
pulses will be dependent on the relative timing between t
edge of
minimum values of these parameters are:
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
POWER-DOWN CONTROL
If the PDN bit is set to 1, the
device will run normally.
POWER-DOWN
If
events in the following sequence:
1. Disable OUT (same sequence as when OE is used) and reset N counters.
2. When OUT is low, switch OUT to high-impedance state.
3. Disable MCLK (and OUT0 if
4. Disable internal oscillator and OSCIN buffer.
Ehigh
PDN
period on the output after the rising edge of
t
t
t
t
LOW
LOW
SIE
SIE
is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to execute
SELX
(min) = t
(max) = 3t
(min) = t
(max) = 3t
and the first rising edge of the externally derived clock is t
I
/2
I
I
/2
/2 + t
I
/2 + t
Ehigh
Elow
PDN
EN0
/
SELX
SELX
bit = 0), switch OUT0 to high impedance state.
SELX
pin can be used to power-down the device. If
is high and a low level is sensed on EXTCLK, OUT0 will be
signal and the external clock, there may be up to one full
8 of 18
SELX
. Then, the “low” time (t
I
and t
SELX
E
. The time interval between the falling
pin. In this case the switch is level
SIE
. Approximate maximum and
LOW
) between output
PDN
is high the