ISL12026IVZ-T Intersil, ISL12026IVZ-T Datasheet
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ISL12026IVZ-T
Specifications of ISL12026IVZ-T
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ISL12026IVZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2005, 2006, 2007, 2008, 2010. All Rights Reserved. Intersil (and design) and BlockLock are trademarks owned by Intersil Corporation or one of its subsidiaries. ISL12026, ISL12026A FN8231.9 ...
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... Ordering Information PART NUMBER PART (Notes MARKING ISL12026IBZ 12026 IBZ ISL12026IVZ 2026 IVZ ISL12026AIBZ 12026A IBZ ISL12026AIVZ 2026A IVZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Output Low Voltage OL I Output Leakage Current LO 3 ISL12026, ISL12026A Thermal Information OUT Pins Thermal Resistance (Typical SOIC Package (Notes TSSOP Package (Notes Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +2.7V to +5.5V 3.3V. DD CONDITIONS CONDITIONS ...
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EEPROM Specifications PARAMETER EEPROM Endurance Temperature ≤ +75°C EEPROM Retention 2 Serial Interface (I C) Specifications DC Electrical Specifications SYMBOL PARAMETER V SDA and SCL Input Buffer LOW IL Voltage V SDA and SCL Input Buffer HIGH IH Voltage Hysteresis ...
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AC Electrical Specifications (Continued) SYMBOL PARAMETER t STOP Condition Set-up Time SU:STO t STOP Condition Hold Time for HD:STO Read or Volatile Only Write t Output Data Hold Time DH Cpin SDA and SCL Pin Capacitance t Non-volatile Write Cycle ...
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Write Cycle Timing SCL SDA 8TH BIT OF LAST BYTE Typical Performance Curves 4.0 BSW = 3.5 SCL, SDA PULL-UPS = 0V 3.0 2.5 2.0 1.5 SCL, SDA PULL-UPS = V 1.0 0.5 BSW = 0 OR ...
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Typical Performance Curves 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.8 2.3 2.8 3.3 3.8 V (V) DD FIGURE DD3 Description The ISL12026 device is a Real Time Clock with clock/ calendar, two ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information, see “ ...
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The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The ...
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ADDR. TYPE REG NAME 7 003F Status SR BAT 0037 RTC Y2K 0 (SRAM) 0036 DW 0 0035 YR Y23 0034 MO 0 0033 DT 0 0032 HR MIL 0031 MN 0 0030 SC 0 0014 Control PWR SBIB (EEPROM) ...
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TABLE 3. PROTECTED ADDRESSES ISL12026 None (Default 180 – 1FF 100 – 1FF 000 – 1FF 000 – 03F ...
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DTR Register - DTR2, DTR1, DTR0: Digital Trimming Register The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DTR2 is a sign bit. DTR2 = ...
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... Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for years. Another option is to use a SuperCap for applications where V for month. See “Application Section” on page 19 for more information ...
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The ISL12026 device will switch from the V when one of the following conditions occurs: - Condition 1: V > BAT BATHYS ≈ 50mV where V BATHYS - Condition 2: V > ...
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SCL SDA SCL SDA SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER In the read mode, the device will transmit 8 bits of data, release the SDA line, then monitor ...
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DEVICE IDENTIFIER ARRAY CCR FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (16 BYTE PAGES) SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE Following the Slave Byte ...
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Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” ...
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Acknowledge Polling Disabling of the inputs during non-volatile write cycles can be used to take advantage of the 12ms (typ) write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the ...
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... DATA K (1) (2) FIGURE 22. SEQUENTIAL READ SEQUENCE The Intersil RTC family uses an oscillator circuit with on-chip crystal compensation network, including adjustable load-capacitance. The only external component required is the crystal. The compensation network is optimized for operation with certain crystal parameters which are common in many of the surface mount or tuning-fork crystals available today ...
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... Figure 23 minimizes this by running the IRQ/F away from the X1 and X2 pins. Also, reducing the switching current at this pin by careful selection of the pull-up resistor value will reduce noise. Intersil suggests a minimum value of 5.1kΩ for 32.768kHz, and higher values (up to 20kΩ) for lower frequency IRQ/F ...
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... Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a SuperCap for applications where V may disappear intermittently for DD short periods of time ...
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BIT ALARM0 REGISTER HEX SCA0 B0h Seconds set to 30, MNA0 00h Minutes disabled HRA0 0 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing M8.173 8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 01/ 3.0 ±0 4.40 ±0. PIN 1 ID MARK 1 0. 0.65 TOP VIEW H C ...