AD9975BST Analog Devices Inc, AD9975BST Datasheet

IC FRONT-END MIXED-SGNL 48-LQFP

AD9975BST

Manufacturer Part Number
AD9975BST
Description
IC FRONT-END MIXED-SGNL 48-LQFP
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Datasheet

Specifications of AD9975BST

Rohs Status
RoHS non-compliant
Number Of Bits
10
Number Of Channels
1
Voltage - Supply, Analog
3.3V
Voltage - Supply, Digital
3.3V
Package / Case
48-LQFP
Power (watts)
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9975BST
Manufacturer:
ADI
Quantity:
364
a
GENERAL DESCRIPTION
The AD9975 is a single-supply, broadband modem, mixed
signal, front end (MxFE™) IC. The device contains a transmit
path interpolation filter and DAC and a receive path PGA,
LPF, and ADC required for a variety of broadband modem
applications. Also on-chip is a PLL clock multiplier that pro-
vides all required clocks from a single crystal or clock input.
The TxDAC+ uses a digital 2× interpolation low-pass filter to
oversample the transmit data and ease the complexity of analog
reconstruction filtering. The transmit path bandwidth is 21 MHz
when sampled at 100 MSPS. The 10-bit DAC provides differen-
tial current outputs. The DAC full-scale current can be adjusted
from 2 to 20 mA by a single resistor, providing 20 dB of additional
gain range.
The receive path consists of a PGA, LPF, and ADC. The program-
mable gain amplifier (PGA) has two modes of operation. One
mode allows programming through the serial port and provides a
gain range from –6 dB to +36 dB in 2 dB steps. The other mode
allows the gain to be controlled through an asynchronous 3-pin
port and offers a gain range from 0 dB to 48 dB in 8 dB steps
with the use of an external gain stage. The receive path LPF
cutoff frequency can be selected to either 12 MHz or 26 MHz.
TxDAC+ is a registered trademark and MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FEATURES
Low Cost, 3.3 V-CMOS, Mixed Signal, Front End
10-Bit D/A Converter (TxDAC+
10-Bit, 50 MSPS A/D Converter
Internal Clock Multiplier (PLL)
Two Auxiliary Clock Outputs
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
Converter for Broadband Modems
50 MSPS Input Word Rate
2
100 MSPS DAC Output Update Rate
Wide (21 MHz) Transmit Bandwidth
Power-Down Modes
Fourth Order LPF with Selectable Cutoff Frequency
Dual Mode Programmable Gain Amplifier
Interpolating Low-Pass Transmit Filter
®
)
The filter cutoff frequency can also be tuned or bypassed where
filter requirements differ. The 10-bit ADC uses a multistage
differential pipeline architecture to achieve excellent dynamic
performance with low power consumption.
The digital transmit and receive ports are multiplexed onto a
10-bit databus and have individual TX/RX clocks and TX/RX
enable lines. This interface connects directly to Homelug 1.0
PHY/MAC chips from Intellon and Conexant.
The AD9975 is available in a space-saving 48-lead LQFP pack-
age. The device is specified over the commercial (–40°C to
+85°C) temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
ADIO[9:0]
AGC[2:0]
RXCLK
SPORT
TXCLK
RXEN
TXEN
3
3
FUNCTIONAL BLOCK DIAGRAM
AD9975
REGISTER
CONTROL
10
10
Mixed-Signal Front End
ADC
Broadband Modem
K
PGA
CLK-GEN
10
© Analog Devices, Inc., 2002
LPF
AD9975
TxDAC+
www.analog.com
PGA
TX+
TX–
CLK1
CLK2
RX+
RX–
OSCIN
XTAL

AD9975BST Summary of contents

Page 1

FEATURES Low Cost, 3.3 V-CMOS, Mixed Signal, Front End Converter for Broadband Modems 10-Bit D/A Converter (TxDAC+ 50 MSPS Input Word Rate 2 Interpolating Low-Pass Transmit Filter 100 MSPS DAC Output Update Rate Wide (21 MHz) Transmit Bandwidth Power-Down ...

Page 2

AD9975–SPECIFICATIONS Parameter OSC IN CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Impedance CLOCK OUTPUT CHARACTERISTICS CLKA Jitter (F Derived from PLL) CLKA CLKA Duty Cycle TX CHARACTERISTICS 2× Interpolation Filter Characteristics TX Path Latency, 2× Interpolation Pass-Band Flatness 0 ...

Page 3

Parameter RX PATH LPF (Low Cutoff Frequency) Cutoff Frequency Cutoff Frequency Variation Attenuation @ 22 MHz Pass-Band Ripple Group Delay Variation Settling Time (to 1% FS, Min to Max Gain Change) Total Harmonic Distortion at Max Gain (THD) RX PATH ...

Page 4

AD9975 SPECIFICATIONS (continued) Parameter SERIAL CONTROL BUS Maximum SCLK Frequency (f ) SCLK Clock Pulsewidth High (t ) PWH Clock Pulsewidth Low (t ) PWL Clock Rise/Fall Time Data/Chip-Select Setup Time ( Data Hold Time ( ...

Page 5

Model Temperature Range AD9975ABST –40ºC to +85ºC AD9975ABSTEB –40ºC to +85ºC AD9975ABSTRL –40ºC to +85ºC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge ...

Page 6

AD9975 DEFINITIONS OF SPECIFICATIONS Clock Jitter The clock jitter is a measure of the intrinsic jitter of the PLL generated clocks measure of the jitter from one rising edge of the clock with respect to another edge ...

Page 7

INTERPOLATION FILTER 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 F SAMPLE TPC 1. 2 × Low-Pass Interpolation Filter 10 INTERPOLATION FILTER 0 –10 INCLUDING SIN(X)/X –20 –30 –40 ...

Page 8

AD9975 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10.003 10.004 10.005 10.006 10.007 10.008 10.009 FREQUENCY – MHz TPC 7. Phase Noise Plot @ MHz, 2 × LPF f OUT 10 0 –10 ...

Page 9

VGA GAIN – dB TPC 13. PGA Gain ...

Page 10

AD9975 4000 3800 3600 3400 3200 3000 2800 2600 2400 ADC CLOCK CYCLES TPC 19. Rx Path Settling, 1/2 Scale Rising Step with Gain Change, LPF MHz 4000 3800 ...

Page 11

F – MHz IN TPC 25. Rx Path SNR vs. F Gain = –6 dB, Rx LPF Bypassed REV. 0 –50 –55 –60 –65 ...

Page 12

AD9975 TRANSMIT PATH The AD9975 transmit path consists of a digital interface port, a bypassable 2× interpolation filter, and a transmit DAC. The clock signals required by these blocks are generated by the inter- nal PLL. The block diagram below ...

Page 13

RECEIVE PATH DESCRIPTION The receive path consists of a two stage PGA, a continuous time, 4-pole LPF, an ADC, and a digital HPF. Also working in conjunction with the receive path is an offset correction circuit and a digital phase-locked ...

Page 14

AD9975 DIGITAL HPF Following the ADC, there is a bypassable digital HPF. The response is a single pole IIR HPF. The transfer function is approximately – 99994 ) / ( – ...

Page 15

DIGITAL INTERFACE PORT TIMING The ADIO[9:0] bus accepts input data-words into the transmit path when the TXEN pin is high, the RXEN pin is low, and a clock is present on the TXCLK pin. Figure 3 illustrates the transmit path ...

Page 16

AD9975 SCLK t DV SDATA INSTRUCTION BIT n INSTRUCTION BIT n–1 Figure 6. Timing Diagram Register Read from AD9975 MSB/LSB Transfers The AD9975 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data ...

Page 17

The serial port is operated by an internal state machine and is dependent on the number of SCLK cycles since the last time SENABLE went active. On every eighth rising edge of SCLK, a byte is transferred over the SPI. ...

Page 18

AD9975 Bit 7: RX LPF Tuning Update Disable Setting this bit high disables the automatic background receive filter calibration. The AD9975 automatically calibrates the receive filter on reset and every few (~2) seconds thereafter to compensate for process and temperature ...

Page 19

Bit 1: ADC Output on Falling RXCLK If Bit 1 is set high, the TX path data will be sampled on the falling edge of RXCLK. When this bit is low, the data will be sampled on the rising edge ...

Page 20

AD9975 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 9.00 BSC 0.60 0. ...

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