CS5529-ASZ Cirrus Logic Inc, CS5529-ASZ Datasheet - Page 25
![IC ADC 16BIT W/6BIT LATCH 20SSOP](/photos/6/60/66044/cs5529-asz_sml.jpg)
CS5529-ASZ
Manufacturer Part Number
CS5529-ASZ
Description
IC ADC 16BIT W/6BIT LATCH 20SSOP
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5529-ASZ.pdf
(31 pages)
Specifications of CS5529-ASZ
Number Of Converters
1
Package / Case
20-SSOP
Number Of Bits
16
Data Interface
Serial
Power Dissipation (max)
3.5mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Architecture
Delta-Sigma
Conversion Rate
101 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Maximum Power Dissipation
8 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1015 - EVAL BOARD FOR CS5529
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1110-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS5529-ASZ
Manufacturer:
CIRRUS
Quantity:
88
Part Number:
CS5529-ASZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS5529-ASZR
Manufacturer:
CIRRUS
Quantity:
20 000
Getting Started
The CS5529 has many features. From a software
programmer’s perspective, what should be done
first? To begin, a 32.768 kHz crystal takes approx-
imately 500 ms to start-up. To accommodate for
this, it is recommended that a software delay of ap-
proximately 500 ms to 1 second precede the pro-
cessor’s ADC initialization code before any
registers are accessed in the ADC. This delay time
is dependent on the start-up delay of the clock
source. If a CMOS clock source with no start-up
delay is being used to drive the ADC, then this de-
lay is not necessary.
The converters include an on-chip power on reset
circuit to automatically reset the ADCs shortly af-
ter power up. When power to the CS5529 is ap-
plied, the chip is held in a reset condition until the
32.768 kHz oscillator has started and a counter-
timer elapses. The counter-timer counts 1002 oscil-
lator clock cycles to make sure the oscillator is ful-
ly stable. During this time-out period the serial port
logic is reset and the RV (Reset Valid) bit in the
configuration register is set to indicate that a valid
reset occurred. In normal start-up conditions, this
power-on-reset circuit should reset the chip when
power is applied. If your application may experi-
ence abnormal power start-up conditions, the fol-
lowing sequence of instructions should be
performed to guarantee the converter begins proper
operation:
1) After power is applied, initialize the serial port
2) Write a ‘1’ to the reset bit (RS) of the configu-
3) Read the configuration register to determine if
DS246F5
using the serial port synchronization sequence.
ration register to reset the converter.
4) When the RV bit has been set to ‘1’, reset the
Once the RS bit has been set to ‘0’, the ADC is
placed in the command state were it waits for a val-
id command to execute. The next step is to load the
configuration register. If you need to do a factory
calibration, perform offset and gain calibration
steps. Then off-load the offset and gain register
contents into EEPROM. These registers can then
be initialized to these conditions when the instru-
ment is used in normal operation. Once calibration
is ready, input the command to start conversions in
either single or continuous conversion mode. Mon-
itor the SDO pin for a flag that the data is ready and
read conversion data.
PCB Layout
The CS5529 should be placed entirely over an ana-
log ground plane with the DGND pin of the device
connected to the analog ground plane. If the design
splits the ground plane, place the analog-digital
plane split immediately adjacent to the digital por-
tion of the chip.
the reset valid bit (RV) is set to ‘1’. If the RV
bit is not set, the configuration register should
be read again.
RS bit back to ‘0’ by writing to 0x000000 to the
configuration register. Note that while the RS
bit is set to ‘1’ all other register bits in the ADC
will be reset to their default state, and the RS bit
must be set to ‘0’ for normal operation of the
converters.
CS5529
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