CS5529-ASZ Cirrus Logic Inc, CS5529-ASZ Datasheet - Page 8
![IC ADC 16BIT W/6BIT LATCH 20SSOP](/photos/6/60/66044/cs5529-asz_sml.jpg)
CS5529-ASZ
Manufacturer Part Number
CS5529-ASZ
Description
IC ADC 16BIT W/6BIT LATCH 20SSOP
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5529-ASZ.pdf
(31 pages)
Specifications of CS5529-ASZ
Number Of Converters
1
Package / Case
20-SSOP
Number Of Bits
16
Data Interface
Serial
Power Dissipation (max)
3.5mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Architecture
Delta-Sigma
Conversion Rate
101 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Maximum Power Dissipation
8 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1015 - EVAL BOARD FOR CS5529
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1110-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS5529-ASZ
Manufacturer:
CIRRUS
Quantity:
88
Part Number:
CS5529-ASZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS5529-ASZR
Manufacturer:
CIRRUS
Quantity:
20 000
SWITCHING CHARACTERISTICS
Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C
Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for
8
Master Clock Frequency:
Master Clock Duty Cycle
Rise Times
Fall Times
Start-up
Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Write Timing
CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
increased throughput.
external clock source.
Parameter
External Clock or Internal Oscillator
XTAL = 32.768 kHz (Note 21)
Any Digital Input Except SCLK
Any Digital Input Except SCLK
L
= 50pF)
(T
A
Any Digital Output
Any Digital Output
Pulse Width High
= 25 °C; VA ± = ±2.5 V ±5%, VD+ = 3 V ±5% or 5 V ±5%;
Pulse Width Low
(Note 20)
(Note 20)
(Note19)
SCLK
SCLK
Symbol
SCLK
XIN
t
t
t
t
rise
rise
ost
por
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
Min
250
250
100
100
30
40
50
50
0
-
-
-
-
-
-
-
-
-
-
-
32.768
1002
Typ
500
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
100
150
150
150
1.0
1.0
60
CS5529
2
-
-
-
-
-
-
-
-
-
-
DS246F5
cycles
MHz
Unit
kHz
XIN
ms
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%