ADC1002S020HL/C1,1 NXP Semiconductors, ADC1002S020HL/C1,1 Datasheet - Page 8

• Manufacturer Part Number: ADC1002S020HL/C1,1
• Description: IC ADC 10BIT PAR 20MHZ 32-LQFP
• Manufacturer: NXP Semiconductors

Specifications of ADC1002S020HL/C1,1

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 73mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286648118; ADC1002S020HL/C1-T; ADC1002S020HL/C1-T

NXP Semiconductors
Table 6.
V
together; V
specified.
[1]
[2]
[3]
[4]
[5]
[6]
ADC1002S020_2
Product data sheet
Symbol
Timing (f
t
t
t
3-state output delay times; see
t
t
t
t
Standby mode output delay times
t
t
d(s)
h(o)
d(o)
dZH
dZL
dHZ
dLZ
TLH
THL
DDA
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 1 ns.
Analog input voltages producing code 0 up to and including code 1023:
a) V
b) V
To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors R
a) The current flowing into the resistor ladder is
b) Since R
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
SIgnal-to-Noise And Distortion (SINAD) ratio: SINAD = ENOB
Output data acquisition: the output data is available after the maximum delay time of t
= V7 to V9 = 3.3 V; V
(V
to code 1023 at T
to 1023 is
will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends
mainly on the difference V
parallel and fed with the same reference source, the matching between each of them is optimized.
offset
offset
RB
clk
i(p-p)
) at T
Characteristics
= 20 MHz; C
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
TOP is the difference between the reference voltage on pin RT (V
Parameter
sampling delay time
output hold time
output delay time
float to active HIGH
delay time
float to active LOW delay
time
active HIGH to float
delay time
active LOW to float delay
time
LOW to HIGH transition
time
HIGH to LOW transition
time
L
, R
= 1.83 V; C
amb
V
OB
I
= 25 C.
=
and R
R
amb
L
L
OT
= 25 C
DDD
L
= 20 pF); see
I
= 20 pF; T
have similar behavior with respect to process and temperature variation, the ratio
L
…continued
RT
=
= V4 to V3 = V18 to V19 = 3.3 V; V
.
--------------------------------------- -
R
Figure 5
V
OB
RB
+
and its variation with temperature and supply voltage. When several ADCs are connected in
amb
R
R
Conditions
V
V
stand-by
start-up
L
L
Figure 4
DDO
DDO
+
= 0 C to 70 C; typical values measured at T
R
OT
= 4.75 V
= 3.15 V
I
=
Rev. 02 — 13 August 2008
[6]
V
--------------------------------------- -
R
RT
OB
V
+
RT
+
V
R
–
RB
L
V
6.02 + 1.76 dB.
+
RB
R
=
OT
DDO
OB
0.871
and the full-scale input range at the converter, to cover code 0
and R
= V20 to V21 = 3.3 V; V
RT
) and the analog input which produces data outputs equal
Min
-
5
8
8
-
-
-
-
-
-
OT
V
RT
as shown in
–
d(o)
V
.
RB
Single 10 bits ADC, up to 20 MHz
Typ
-
12
17
14
16
16
14
-
-
-
amb
Figure
ADC1002S020
= 25 C unless otherwise
SSA
3.
, V
SSD
Max
5
-
15
20
18
20
20
18
200
500
--------------------------------------- -
R
OB
© NXP B.V. 2008. All rights reserved.
and V
+
R
R
L
L
SSO
+
R
OT
shorted
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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