MAX197BENI+ Maxim Integrated Products, MAX197BENI+ Datasheet - Page 5

• Manufacturer Part Number: MAX197BENI+
• Description: IC DAS 12BIT SNGL 28-DIP
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX197BENI+

• Resolution (bits): 12 b
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 1143 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Input Voltage: 10 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(V
with 50% duty cycle; T
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
Note 12: t
Note 13: t
CS Pulse Width
WR Pulse Width
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
RD Low to Output Data Valid
HBEN High or HBEN Low to
Output Valid
RD High to Output Disable
RD Low to INT High Delay
DD
Single +5V, 12-Bit DAS with 8+4 Bus Interface
= 5V ±5%; unipolar/bipolar range; external reference mode, V
PARAMETER
Accuracy specifications tested at V
Rejection test. Tested for the ±10V input range.
External reference: V
Ground "on" channel; sine wave applied to all "off" channels.
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Guaranteed by design. Not tested.
Use static loads only.
Tested using internal reference.
PSRR measured at full-scale.
External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
or 2.4V.
DO
TR
is defined as the time required for the data lines to change by 0.5V.
and t
DO1
_______________________________________________________________________________________
A
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
= T
MIN
REF
to T
Multi-Range (±10V, ±5V, +10V, +5V),
SYMBOL
MAX
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
t
t
t
t
CSWH
t
t
CSWS
CSRH
t
t
CSRS
CWS
CWH
t
t
t
DO1
INT1
t
t
t
WR
DH
DO
CS
DS
TR
, unless otherwise noted.)
DD
Figure 2, C
Figure 2, C
(Note 13)
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
L
L
= 100pF (Note 12)
= 100pF (Note 12)
CONDITIONS
REF
= 4.096V; 4.7µF at REF pin; external clock, f
MIN
80
80
60
0
0
0
0
0
TYP
MAX
100
120
120
120
50
70
CLK
= 2.0MHz
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5