MAX197BENI+ Maxim Integrated Products, MAX197BENI+ Datasheet - Page 7

• Manufacturer Part Number: MAX197BENI+
• Description: IC DAS 12BIT SNGL 28-DIP
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX197BENI+

• Resolution (bits): 12 b
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 1143 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Input Voltage: 10 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1. Reference-Adjust Circuit
______________________________________________________________Pin Description
16–23
7–10
PIN
11
12
13
14
15
24
25
26
27
28
1
2
3
4
5
6
100kΩ
Single +5V, 12-Bit DAS with 8+4 Bus Interface
24kΩ
CH0–CH7
+5V
REFADJ
D3/D11
D2/D10
D7–D4
NAME
AGND
DGND
HBEN
SHDN
D1/D9
D0/D8
CLK
REF
V
WR
INT
CS
RD
DD
510kΩ
_______________________________________________________________________________________
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor from this pin to ground to set the internal clock frequency; f
C
Chip Select, active low.
When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.
If CS is low, a falling edge on RD will enable a read operation on the data bus.
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
Three-State Digital I/O
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.
Analog Ground
Analog Input Channels
INT goes low when conversion is complete and output data is ready.
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to V
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to V
+5V Supply. Bypass with 0.1µF capacitor to AGND.
Digital Ground
0.01µF
CLK
DD
= 100pF.
when using an external reference at the REF pin.
Multi-Range (±10V, ±5V, +10V, +5V),
REFADJ
MAX197
DD
.
Figure 2. Load Circuits for Enable Time
FUNCTION
a. HIGH-Z TO V
D
OUT
3kΩ
OH
AND V
OL
TO V
C
LOAD
OH
CLK
= 1.56MHz typical with
b. HIGH-Z TO V
D
OUT
3kΩ
OL
+5V
AND V
C
OH
LOAD
TO V
OL
7