PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 156

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
REGISTER 11-3:
11.1.4
Many of the ports multiplex analog and digital function-
ality, providing a lot of flexibility for hardware designers.
PIC18F87K90 family devices can make any analog pin,
analog or digital, depending on an application’s needs.
The ports’ analog/digital functionality is controlled by
the registers: ANCON0, ANCON1 and ANCON2.
DS39957D-page 156
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-1
bit 0
R/W-0
U2OD
ANALOG AND DIGITAL PORTS
U2OD: EUSART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U1OD: EUSART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
Unimplemented: Read as ‘0’
CTMUDS: CTMU Pulse Delay Enable bit
1 = Pulse delay input for CTMU is enabled on pin, RF1
0 = Pulse delay input for CTMU is disabled on pin, RF1
R/W-0
U1OD
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Setting these registers makes the corresponding pins
analog and clearing the registers makes the ports digi-
tal. For details on these registers, see
“12-Bit Analog-to-Digital Converter (A/D)
U-0
—
U-0
—
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
U-0
—
Section 23.0
CTMUDS
R/W-0
Module”.
bit 0