PIC18F65K90-I/MR Microchip Technology, PIC18F65K90-I/MR Datasheet - Page 43

• Manufacturer Part Number: PIC18F65K90-I/MR
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90-I/MR

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Details

3.2
The OSCCON register
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
REGISTER 3-1:
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
Note 1:
IDLEN
R/W-0
2:
3:
4:
5:
Control Registers
Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
Source selected by the INTSRC bit (OSCTUNE<7>).
Modifying these bits will cause an immediate clock source switch.
INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = HF-INTOSC output frequency is used (16 MHz)
110 = HF-INTOSC/2 output frequency is used (8 MHz, default)
101 = HF-INTOSC/4 output frequency is used (4 MHz)
100 = HF-INTOSC/8 output frequency is used (2 MHz)
011 = HF-INTOSC/16 output frequency is used (1 MHz)
If INTSRC = 0 and MFIOSEL = 0:
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)
If INTSRC = 1 and MFIOSEL = 0:
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = HF-INTOSC/512 output frequency is used (31.25 kHz)
If INTSRC = 0 and MFIOSEL = 1:
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)
If INTSRC = 1 and MFIOSEL = 1:
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = MF-INTOSC/16 output frequency is used (31.25 kHz)
OSTS: Oscillator Start-up Timer Time-out Status bit
1 = Oscillator Start-up Timer (OST) time-out has expired: primary oscillator is running as defined by
0 = Oscillator Start-up Timer (OST) time-out is running: primary oscillator is not ready; device is
IRCF2
R/W-1
OSC<3:0>
running from an internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC)
OSCCON: OSCILLATOR CONTROL REGISTER
(Register
(2)
W = Writable bit
‘1’ = Bit is set
IRCF1
3-1) controls the main
R/W-1
(2)
IRCF0
R/W-0
(3,5)
(3,5)
(3,5)
(3,5)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K90 FAMILY
OSTS
The OSCTUNE register
tuning and operation of the internal oscillator block. It also
implements the PLLEN bit which controls the operation of
the Phase Locked Loop (PLL) (see
Frequency
R
(1)
(1)
(2)
Multiplier”).
HFIOFS
R-0
x = Bit is unknown
(Register
SCS1
R/W-0
(4)
Section 3.5.2 “PLL
3-3) controls the
DS39957D-page 43
SCS0
R/W-0
(4)
bit 0