MT47H64M16HR-25E:E Micron Technology Inc, MT47H64M16HR-25E:E Datasheet - Page 129
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MT47H64M16HR-25E:E
Manufacturer Part Number
MT47H64M16HR-25E:E
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H64M16HR-25EE.pdf
(135 pages)
Specifications of MT47H64M16HR-25E:E
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
320mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
ODT Timing
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Once a 12ns delay (
bled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate either in synchronous mode or asynchronous mode, de-
pending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 79 (page 130).
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]),
in Figure 81 (page 131).
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
t
ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-
rameter
signal satisfies
(MIN) is satisfied,
shows the example where
occur until state T3. When
ODT turn-on timing prior to entering any power-down mode is determined by the pa-
rameter
satisfies
satisfied,
the example where
until state T3. When
ODT turn-off timing after exiting any power-down mode is determined by the parame-
ter
satisfies
satisfied,
the example where
When
ODT turn-on timing after exiting either slow-exit power-down mode or precharge power-
down mode is determined by the parameter
(page 135). At state Ta1, the ODT HIGH signal satisfies
down mode at state T1. When
parameters apply. Figure 86 (page 135) also shows the example where
not satisfied because ODT HIGH occurs at state Ta0. When
t
AONPD and
AONPD timing parameters apply.
t
AXPD (MIN), as shown in Figure 85 (page 134). At state Ta1, the ODT LOW signal
t
AXPD (MIN) is not satisfied,
t
t
t
t
ANPD (MIN), as shown in Figure 83 (page 132). At state T2, the ODT HIGH
ANPD, as shown in Figure 84 (page 133). At state T2, the ODT HIGH signal
ANPD (MIN) prior to entering power-down mode at T5. When
AXPD (MIN) after exiting power-down mode at state T1. When
t
t
AOND and
AOFD and
t
AOND,
t
AOFPD timing parameters are applied, as shown in Figure 82 (page 132).
t
ANPD (MIN) prior to entering power-down mode at T5. When
t
AOFD and
t
t
t
MOD) has been satisfied, and after the ODT function has been ena-
ANPD (MIN) is not satisfied because ODT HIGH does not occur
AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.
t
t
t
ANPD (MIN) is not satisfied,
AON,
t
AOF timing parameters apply. Figure 85 (page 134) also shows
AON timing parameters apply. Figure 84 (page 133) also shows
t
t
ANPD (MIN) is not satisfied,
ANPD (MIN) is not satisfied because ODT HIGH does not
t
AOFD, and
129
t
AOF timing parameters apply. Figure 83 (page 132) also
t
AXPD (MIN) is satisfied,
t
AOFPD timing parameters apply.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
AOF timing parameters are applied, as shown
t
AXPD (MIN), as shown in Figure 86
1Gb: x4, x8, x16 DDR2 SDRAM
t
AONPD timing parameters apply.
t
t
AOFPD timing parameters apply.
AXPD (MIN) after exiting power-
t
AOND and
t
AXPD (MIN) is not satisfied,
© 2004 Micron Technology, Inc. All rights reserved.
t
AON timing
t
AXPD (MIN) is
t
ODT Timing
t
ANPD (MIN) is
AXPD (MIN) is
t
ANPD