MT47H64M16HR-25E:E Micron Technology Inc, MT47H64M16HR-25E:E Datasheet - Page 90

• Manufacturer Part Number: MT47H64M16HR-25E:E
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-25E:E

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 320mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Notes:
1. Applying power; if CKE is maintained below 0.2 × VddQ, outputs remain disabled. To
2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de-
3. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE com-
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is re-
guarantee Rtt (ODT resistance) is off, Vref must be valid and a low level must be applied
to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than
VddQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). Vtt is not ap-
plied directly to the device; however,
least one of the following two sets of conditions (A or B) must be met to obtain a stable
supply state (stable supply defined as Vdd, VddL, VddQ, Vref, and Vtt are between their
minimum and maximum values as stated in Table 12 (page 42)):
A. Single power source: The Vdd voltage ramp from 300mV to Vdd (MIN) must take no
longer than 200ms; during the Vdd voltage ramp, |Vdd - VddQ| ≤ 0.3V. Once supply volt-
age ramping is complete (when VddQ crosses Vdd [MIN]), Table 12 (page 42) specifica-
tions apply.
• Vdd, VddL, and VddQ are driven from a single power converter output
• Vtt is limited to 0.95V MAX
• Vref tracks VddQ/2; Vref must be within ±0.3V with respect to VddQ/2 during supply
• VddQ ≥ Vref at all times
B. Multiple power sources: Vdd ≥ VddL ≥ VddQ must be maintained during supply volt-
age ramping, for both AC and DC levels, until supply voltage ramping completes (VddQ
crosses Vdd [MIN]). Once supply voltage ramping is complete, Table 12 (page 42) specifi-
cations apply.
• Apply Vdd and VddL before or at the same time as VddQ; Vdd/VddL voltage ramp
• Apply VddQ before or at the same time as Vtt; the VddQ voltage ramp time from
• Vref must track VddQ/2; Vref must be within ±0.3V with respect to VddQ/2 during sup-
• Apply Vtt; the Vtt voltage ramp time from when VddQ (MIN) is achieved to when Vtt
vice power-up prior to Vref being stable. After state T0, CKE is required to have SSTL_18
input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of
the initialization sequence.
commands, then take CKE HIGH.
LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropri-
ate self refresh rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2
(EMR2) (page 86) for all EMR(2) requirements).
HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3
(EMR3) (page 87) for all EMR(3) requirements.
mand, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set
to “0” or “1;” Micron recommends setting them to “0;” remaining EMR bits must be
“0.” Extended Mode Register (EMR) (page 82) for all EMR requirements.
quired to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to
ramp time; does not need to be satisfied when ramping power down
time must be ≤ 200ms from when Vdd ramps from 300mV to Vdd (MIN)
when Vdd (MIN) is achieved to when VddQ (MIN) is achieved must be ≤ 500ms; while
Vdd is ramping, current can be supplied from Vdd through the device to VddQ
ply ramp time; VddQ ≥ Vref must be met at all times; does not need to be satisfied
when ramping power down
(MIN) is achieved must be no greater than 500ms
90
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
VTD should be ≥0 to avoid device latch-up. At
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
Initialization