MT47H64M16HR-25E:E Micron Technology Inc, MT47H64M16HR-25E:E Datasheet - Page 6

• Manufacturer Part Number: MT47H64M16HR-25E:E
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-25E:E

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 320mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

1Gb: x4, x8, x16 DDR2 SDRAM
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17
Table 4: Input Capacitance ............................................................................................................................ 22
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 23
Table 6: Temperature Limits .......................................................................................................................... 24
Table 7: Thermal Impedance ......................................................................................................................... 25
Table 8: General Idd Parameters .................................................................................................................... 26
Table 9: Idd7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................ 27
Table 10: DDR2 Idd Specifications and Conditions (Die Revisions E and G) ..................................................... 28
Table 11: AC Operating Specifications and Conditions .................................................................................... 31
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 42
Table 13: ODT DC Electrical Characteristics ................................................................................................... 43
Table 14: Input DC Logic Levels ..................................................................................................................... 44
Table 15: Input AC Logic Levels ..................................................................................................................... 44
Table 16: Differential Input Logic Levels ........................................................................................................ 45
Table 17: Differential AC Output Parameters .................................................................................................. 47
Table 18: Output DC Current Drive ................................................................................................................ 47
Table 19: Output Characteristics .................................................................................................................... 48
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 49
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 50
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 51
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 52
Table 24: Input Clamp Characteristics ........................................................................................................... 53
Table 25: Address and Control Balls ............................................................................................................... 54
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 54
Table 27: AC Input Test Conditions ................................................................................................................ 55
t
t
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (
IS and
IH) ................................................... 57
t
t
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (
IS and
IH) .......................................... 58
t
t
Table 30: DDR2-400/533
DS,
DH Derating Values with Differential Strobe ..................................................... 61
t
t
Table 31: DDR2-667/800/1066
DS,
DH Derating Values with Differential Strobe ............................................ 63
t
t
Table 32: Single-Ended DQS Slew Rate Derating Values Using
DS
and
DH
.................................................. 64
b
b
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-667 ...................................... 64
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-533 ...................................... 65
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at Vref) at DDR2-400 ...................................... 65
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 70
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 71
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 73
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 74
Table 40: Burst Definition .............................................................................................................................. 79
Table 41: READ Using Concurrent Auto Precharge ........................................................................................ 100
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 106
Table 43: Truth Table – CKE ......................................................................................................................... 121
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
Rev. O 9/08 EN
© 2004 Micron Technology, Inc. All rights reserved.