CY7C53120L8-44AXI Cypress Semiconductor Corp, CY7C53120L8-44AXI Datasheet

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CY7C53120L8-44AXI

Manufacturer Part Number
CY7C53120L8-44AXI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C53120L8-44AXI

Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C53120L8-44AXI
Quantity:
5 000
Cypress Semiconductor Corporation
Document #: 38-10002 Rev. *E
Features
Note:
1. Maximum junction temperature is 105°C. T
• 3.3V operation
• Three 8-bit pipelined processors for concurrent
• Hardware UART/SPI interface
• Eleven-pin I/O port programmable in 38 modes for fast
• Two 16-bit timer/counters for measuring and gener-
• Five-pin communication port that supports direct
• Programmable pull-ups on IO4–IO7 and 20-mA sink
• Unique 48-bit Neuron ID number in every device to facil-
• 0.35-µm Flash process technology
• On-chip LVD circuit with programmable trip point and
• Programmable Pulse Stretching reset
• 4,096 bytes of SRAM for buffering network data,
• 2.75 KBytes (CY7C53150L), 8KBytes (CY7C53120L8) of
• Addresses up to 56 KBytes of external memory
• 16 KBytes (CY7C53120L8) of ROM containing LonTalk
• Maximum input clock operation of 20MHz over –40°C
• 64-pin TQFP package (CY7C53150L)
• 32-pin SOIC or 44-pin TQFP package (CY7C53120L8)
Logic Block Diagram
processing of application code and network traffic
application program development. I/O port is 5V input
tolerant
ating I/O device waveforms
connect and network transceiver interfaces, and
operates at 3.3V or 5V
current on IO0–IO3
itate network installation and management
digital filter settings
system, and application data storage
Flash memory with on-chip charge pump for flexible
storage of configuration data and application code
(CY7C53150L)
network protocol firmware
to 85°C
[1]
temperature range
Control Processor
(CY7C53120L8)
Media Access
Application
Processor
Processor
4KBytes RAM
Flash
Network
ROM
Junction
= T
Ambient
3901 North First Street
+ V•I•θ
3.3V Neuron
JA
Address Bus
. 32-pin SOIC θ
Data Bus
Internal
Internal
(0:15)
(0:7)
Functional Description
The 3.3V Neuron
version of the 5V Neuron chip with a number of feature
enhancements. The CY7C53120L8/3150L Neuron chip imple-
ments a device for LonWorks
networks. It incorporates, on a single chip, the necessary
communication and control functions, both in hardware and
firmware, that facilitate the design of a LonWorks device.
The CY7C53120L8/3150L supports all the functionality of the
5V CY7C531x0 Neuron chip. Additionally it features 4KBytes
of RAM, 8KBytes of Flash memory (CY7C53120L8), and
hardware UART/SPI. The CY7C53120L8/3150L has an 11-pin
configurable I/O block. The I/Os are all 5V-tolerant to allow
interfacing to TTL Compatible 5V components and microcon-
trollers.
The CY7C53120L8/3150L contains a very flexible five-pin
communication port that can be configured to interface with a
wide variety of media transceivers at a wide range of data
rates. The communication port can operate at either 3.3V or
5V. In 5V mode the communication port is completely
backward compatible with existing 5V transceivers. The most
common transceiver types are twisted-pair, powerline, RF, IR,
fiber-optics, and coaxial.
The CY7C53150L incorporates an external memory interface
that can address up to 56KBytes with 8KBytes of the address
space mapped internally. LonWorks devices that require large
application programs can take advantage of this external
memory capability.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in 16KBytes ROM (CY7C53120L8), or off-chip memory
(CY7C53150L). The firmware also contains 38 prepro-
grammed I/O drivers, simplifying application programming.
The application program is stored in the Flash memory
(CY7C53120L8) and/or off-chip memory (CY7C53150L), and
may be updated by downloading over the network.
JA
= 61.07°C/W. 44-pin TQFP θ
®
Chip Network Processor
Two Timer/Counters
San Jose
4-pin UART/SPI
External Address and
Communications
Data Bus (CY7C53150L)
I/O Block
chip (CY7C53120L8/3150L) is a low-power
Clock, and
Oscillator,
Control
Port
,
JA
CA 95134
= 69.5°C/W. 64-pin TQFP θ
distributed intelligent control
Revised November 2, 2004
SERVICE
CLK1
CLK2
RESET
CP4
CP0
CY7C53120L8
CY7C53150L
IO10
:
IO7
IO6
:
IO0
408-943-2600
JA
= 56.15°C/W.

CY7C53120L8-44AXI Summary of contents

Page 1

... Services at every layer of the OSI networking reference model  are implemented in the LonTalk firmware-based protocol stored in 16KBytes ROM (CY7C53120L8), or off-chip memory (CY7C53150L). The firmware also contains 38 prepro- grammed I/O drivers, simplifying application programming. The application program is stored in the Flash memory (CY7C53120L8) and/or off-chip memory (CY7C53150L), and may be updated by downloading over the network ...

Page 2

... No Connect (NC) — should not be used. (These pins may be used for internal testing.) 3. The smaller dimple at the bottom left of the marking indicates pin 1. Document #: 38-10002 Rev. *E CY7C53150L 64-lead Thin Quad Flat Pack CY7C53150L-64AI CY7C53120L8 CY7C53150L 32 CP4 CP3 31 30 CP2 29 CP1 28 CP0 [ CLK1 24 23 CLK2 ...

Page 3

... CP1 IO3 43 CP0 [ CP2 1 PIN 1 INDICATOR Pin Function CY7C53120L8 CY7C53150L 44-lead TQFP CY7C53120L8-44AI CY7C53150L CY7C53120L8 TQFP-64 SOIC-32 Pin No. Pin No 10, 11, 12 30, 29, 28 14, 15, 16 27, 26 [2] NC CP1 CP0 CV DD CP2 [ CLK1 CLK2 V SS [2] NC CY7C53120L 8 TQFP-44 Pin No 42, 36, 35, 32 31, 30, 27 ...

Page 4

... Memory Usage All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120L8, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150L, the system firmware must be present in the first 16KBytes of an off-chip nonvolatile memory such as Flash, EPROM, EEPROM, or NVRAM ...

Page 5

... RESET is an Input/Output pin 5V-tolerant input pin. It can provide 5V-compatible levels when output if an external resistor is connected between pin and 5V supply. Note: 6. Please see document Errata for CY7C53150L and CY7C53120L8 - 3.3V Neuron Chip (38-17019) for details. Document #: 38-10002 Rev. *E CY7C53120L8 Hardware Serial Communication Engine The CY7C53120L8/3150L features a hardware Serial Communication Engine ...

Page 6

... Filter ( Receiver across hysteresis) Filter ( 5V, there will be a ≥ Differential Receiver (End-to-End) Absolute Symmetry Filter (F) Hysteresis ( Time from input switching states from high to low to output switching states. PHL CY7C53120L8 CY7C53150L [7] V Min. V Typ. hys hys 0.019 V 0.027 0.038 V 0.054 ...

Page 7

... LVI Trip Point ( Part Number CY7C53120L8, and CY7C53150L Notes: 12. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150L, standard outputs also include A0–A15, D0–D7, E, and R/W. 13. IO4–IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up. ...

Page 8

... DC drop across CP2 and CP3 pads @40mA current} / 40mA for CVdd +/-5%. 0 Document #: 38-10002 Rev. *E ± 10% DD Description [16] [18, 19] [20] [19 – t – acc cyc AD DSR [21 200 mV) [22] [21 200 mV) [22] CY7C53120L8 CY7C53150L (V = 3. –40°C to+ 85° Min. Max. 100 3200 t /2 – cyc cyc t /2 – cyc cyc — ...

Page 9

... Document #: 38-10002 Rev for for A0–A15, D0–D7, and R for all other signals 2.0V 0.8V 2.0V 0. 2.0V 0.8V V – – Measured high output drive level OH V – Measured low output drive level OL V TEST SIGNAL 1.4mA L LOAD CY7C53120L8 CY7C53150L PW EL 2.0V /2 Page ...

Page 10

... Figure 7. External Memory Interface Timing Diagram Document #: 38-10002 Rev Address DSR Data In t DHR t t DDW DHR t DHZ Memory READ Memory WRITE CY7C53120L8 CY7C53150L t AD Address Address DDW t t DDZ DDZ t DHZ t DHW t DHW Data Out Data Out Memory WRITE Page ...

Page 11

... Common-Mode voltage: Vcm = ( V(CP0) + V(CP1 Hysteresis Voltage [Vtrip+] - [Vtrip-] Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 3.3V Operation Document #: 38-10002 Rev V(CP0 V(CP1) V(CP0)-V(CP1) 1 Vtrip+ Vtrip V(CP0 V(CP1) V(CP0)-V(CP1) Vtrip+ Vtrip- CY7C53120L8 CY7C53150L Time Time 5V 0V Time Time 3.3V 0V Page ...

Page 12

... Thin Plastic Quad Flat Pack (14 × 14 × 1.4 mm) A65 Document #: 38-10002 Rev. *E Max. Input ROM SRAM Clock (KBytes) (KBytes) (MHz CY7C53120L8 CY7C53150L Package Name Package Type A65 64-lead Thin Plastic Quad Flat Pack S34 32-lead (450 mil) Molded SOIC A44 44-lead Thin Plastic Quad Flat Pack 51-85046-*B Page ...

Page 13

... Cypress against all charges. 44-lead Thin Plastic Quad Flat Pack A44 32-Lead (450 MIL) Molded SOIC S34 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.004[0.102] MIN. SEATING PLANE CY7C53120L8 CY7C53150L 51-85064-*B 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*B Page ...

Page 14

... Clarified Reset Stretch times Corrected pin definitions (pins 10 to 14) on 100pin TQFP diagram Added Theta-JA value for the 100-pin TQFP package Changed part numbers to CY7C53120L8 / CY7C53150L Added ordering information table TGE Add footnote #4 on Power supply considerations Corrected Theta-JA values for all packages ...

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