CY7C53120L8-44AXI Cypress Semiconductor Corp, CY7C53120L8-44AXI Datasheet - Page 5

• Manufacturer Part Number: CY7C53120L8-44AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C53120L8-44AXI

• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Document #: 38-10002 Rev. *E
able to aggregate writes to eight successive address locations
into a single write for CY7C53120L8 devices. For example, if
8KBytes of code is downloaded over the network, the firmware
would execute only 1024 writes rather than 8,192.
Manufacturer ID
The manufacturer ID is 0x02 for both the CY7C53150L and
CY7C53120L8. The major model ID is 0x02 for the
CY7C53150L and 0x10 for the CY7C53120L8. The minor
model ID is 0x08 for both ICs.
Low-Voltage Inhibit (LVI) Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip
reset circuit whenever the V
The default value of the LVI trip point is 2.77V, with a variation
of ±100mV across process and temperature. Every time power
is reapplied to the chip, the LVI trip point gets set to this default
value. Through the application code, the trip point can be
programmed to be one of 16 points between 2.77V and 3.19V.
The purpose of the LVI circuit is to prevent the corruption of
nonvolatile memory during voltage drops. A lower value of trip
point voltage decreases the likelihood of the LVI tripping due
to noise on V
circuits with a lot of noise on the power supply. In circuits that
do not have excessive noise it is recommended that the LVI
trip point be increased which results in better flash protection
in case of real power loss scenarios.
Internal circuitry is provided to ensure that in a power loss
scenario, writes to non-volatile memory that have already
started get completed. To ensure proper functioning of this
circuitry, the V
loss) should be at least 10ms from the time LVI circuit trips and
voltage reaches 2.77V.
The LVI also features a programmable digital filter used to filter
out V
bility of the LVI being triggered by the noise as opposed to true
power loss events. The digital filter is programmable to a value
between 16 and 128 clock cycles. The value chosen depends
on the frequency of the V
should slightly exceed the minimum frequency noise seen on
V
Reset Stretching
At Power-on, the CY7C53120L8/3150L provides internal
Reset Stretching of 25ms at 20MHz clock frequency. Power-on
Reset Stretch time scales with frequency. After Power-on,
Reset Stretch is 50ms independent of frequency of operation.
At Power-on the CY7C53120L8/3150L defaults to Reset
Stretch enabled. The Reset Stretch can either be left enabled
or disabled through software. Reset Stretching eliminates the
need for an external pulse stretching LVI which is required
when using the CY7C53150 with an external Flash memory.
5V-Tolerant Reset
RESET is an Input/Output pin. It is a 5V-tolerant input pin. It
can provide 5V-compatible levels when output if an external
resistor is connected between pin and 5V supply.
Note:
6. Please see document Errata for CY7C53150L and CY7C53120L8 - 3.3V Neuron Chip (38-17019) for details.
DD
. The LVI digital filter defaults to 128 clock cycles.
DD
noise. This is another method of decreasing the possi-
DD
DD
. A lower setting is therefore recommended for
droop time (during power down or power
DD
noise where the digital filter period
DD
input drops below a set value.
Hardware Serial Communication Engine
The CY7C53120L8/3150L features a hardware Serial
Communication Engine. The hardware engine is capable of
performing high-speed communications in either SPI or UART
mode.
Serial Peripheral Interface (SPI) Mode
SPI mode is 4-pin synchronous serial communications
interface that can be set as either a Master or a Slave
SPI communication is a point-to-point or point-to-multi-point
interface that can be configured as master/slave, single-
master/multiple-slaves or multiple-masters/single-slave. The
master initiates all communication between slave and master.
The master drives the SPSCK signal, which is a clock used to
synchronize all data communication between master and
slave.
Slave Select (SS) is an input to the Neuron chip in both the
Master and the Slave modes. In Slave mode, SS is active low
with the Slave communicating only when SS is low. In Master
mode, the SPI engine functions only when the SS signal is
held high. SS can be hard wired high or low or it can be wired
to signals being generated from other sources. The Neuron
Chip can use IO0 through IO6 for selecting between multiple
slaves when acting as a master.
MOSI and MISO are used to send and receive data over SPI.
MOSI is a data output in Master mode and is an input in Slave
mode. MISO is an input in Master mode and is an output in
Slave mode. The phase and polarity of the data relative to the
clock signal is programmable and can be configured in four
possible modes.
The SPI interface can communicate at a maximum of 5Mbps
data rate with a 20-MHz input clock frequency. The maximum
data rate scales with frequency. The data rate is program-
mable and can be scaled by selecting the desired divisor
ranging from 2 to 256 in multiples of 2.
Serial Communication Interface (UART) Mode
UART mode provides a full-duplex asynchronous NRZ format
serial interface for communicating with other devices with
either an UART or UART interface. The UART interface is
optimized to provide industry standard UART baud rates from
the CY7C53120L8/3150L crystal clock rates.
IO7
IO8
IO9
IO10
IO8
IO10
UART Pin
SPI Pin
Slave Select (SS)
Hardware SPI Serial Clock (SPSCK)
Master Input/Slave Output (MISO)
Master Output/Slave Input (MOSI)
Receive Data (RXD)
Transmit Data (TXD)
Description
Description
CY7C53120L8
CY7C53150L
Page 5 of 14
[6]
.