CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 10

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

The CFG area shown in Table 6-2 is used for programming the
NDC via a 64-bit CFG register.
Table 6-2. Configuration and Status Registers Area
6.2
6.2.1
The 64-bit CFG register contains the following fields, as shown
in Table 6-3.
Table 6-3. Configuration Register
SRST. This active high bit resets the state of the device. The
reset bit will be active for 32 CLK cycles and will be
automatically cleared after the reset has taken effect. The
Configuration Register and other internal registers get reset to
their default values and the appropriate values have to be re-
written to the registers after the software reset.
Table Size (TLSZ). This determines the NSE CFG for the
specific table size.
Latency of Hit Signals (HLAT). This determines the data
access latency of associated data SSRAM.
CPCFG. This field sets the width of the processor and context
IDs that will be driven on the CPID bus after the completion of
the operation. The contents of the CPID bus are generated by
concatenating LSBs of the processor ID and the LSBs of the
context ID.
SSRAM Present. This field informs the coprocessor whether
the associative data SSRAM is connected to the NSE (bit is
set to 1; see Figure 13-1) or connected to the network
processor SRAM interface (bit is set to 0; see Figure 13-2).
INTR_Polarity. This bit controls the polarity of the
INTR/INTR_L signal. When this signal is high, the
INTR/INTR_L signal is active high. When this signal is low, the
INTR/INTR_L signal is active low.
Notes:
Document #: 38-02043 Rev. *C
5.
6.
7.
ADR
0–1
Once the NDC is configured, the network processors will use the operating registers area to configure the NSEs, initialize and manage the protocol layer tables,
and perform searches through such tables.
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Learn.
(More details on this field can be found in the data sheets for CYNSE70XXX NSEs.)
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Read
from the SSRAMs. (More details on this field can be found in the data sheet on CYNSE70XXX NSEs.)
Configuration and Status Registers
Configuration Register
00: CPID[7:0] = {processor ID[2:0], context ID[4:0]}.
01: CPID[7:0] = {processor ID[3:0], context ID[3:0]}.
10: CPID[7:0] = {processor ID[4:0], context ID[2:0]}.
11: Reserved.
Reserved External Trans-
63–12
[6]
Address
10–511
0–1
2–3
4–5
6–7
8–9
ceiver Present
11
[5]
Bit in Data Field
Search Result
[7]
10
CFG Register
Error, Status Registers (Read-only)
Mask Registers
Reserved
Information Registers (Read-only)
Reserved
Configuration Register [63:0]
INTR_Polarity
9
Configuration and Status Registers Area
Search Result Bit in Data Field. If this bit is set to 1, the Hit
or Miss information will be attached to the associative data
field in bit 63. This bit has significance only when associative
SSRAM is present (see Result Register 1 for the Search
command). This bit does not replace the hit bit located in
Result Register 0.
External Transceiver Present. If an external transceiver is
used to drive several NSE devices, this bit should be set to 1.
6.2.2
The error and status register is 64 bits wide. Table 6-4 shows
the bit positions of the error status register. The errors shown
in Table 6-5 will be detected by the NDC and the
corresponding error bit will be set in the error and status
register. Once it is Read, the error and status register will be
cleared.
Error Bits. The error bits field holds the type of error. In the
case of multiple errors, multiple error bits may be set. The
context descriptor index will contain the index where the last
error occurred. When an error occurs, the error bit is set along
with the done bit in Result Register 0. The class and type of
error (soft error [SE] or hard error [HE]) are indicated in the
error and status register. When an error occurs, the INTR
signal is asserted and a corresponding error bit is set along
with the context descriptor index to identify the erroneous
command. The interrupt signal is programmable as active low
or active high depending upon the system requirement. See
the description of the CFG register for further detail.
Error and Status Register
SSRAM
Present
8
CPCFG
7–6
HLAT
5–3
CYNCP80192
TLSZ
2–1
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SRST
0