CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 19

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

activate the STRB signal for one CLK cycle. This STRB signal
interrupts and the CPID identifies the context and/or processor
for which the result are Ready. The context within that
processor can wake up and Read the results (Result Register
0 and 1) from the appropriate descriptor. Reading of these
registers by the network processor will reset the done bit. This
descriptor entry is free and may now be used for another
command.
8.0
Procedure
On power-up (boot), the network processor will apply the
following sequence of operations.
8.1
The CYNCP80192 coprocessor generates the reset for the
CYNSE70XXX devices connected to it. It has an input reset
signal (IRST_L) and an output reset signal (ORST_L). The
ORST_L is typically connected to the RST_L input of the
NSE70XXX
CYNCP80192 is as follows:
Document #: 38-02043 Rev. *C
1. Write SRST to 1 in the CFG register.
2. Wait at least 32 cycles, then poll on SRST. After reset has
3. Write the appropriate values into the CFG register and the
4. Write the CFG registers to each of the NSEs, starting with
5. Write the CFG registers of the last NSE in the depth-cas-
6. The descriptor block is now Ready for use by the network
• ORST_L is a synchronous reset that follows IRST_L.
taken effect, the SRST bit will be cleared and all registers
will be reset to their default values.
mask register.
the one residing at the least significant address.
caded system, setting the LDEV and LRAM bits to a 1.
processor(s) for building, managing, and/or searching the
database.
CYNCP80192 Reset Operation
NDC Subsystem Power-up Initialization
family
device.
The
reset
operation
of
In order to reset CYNSE70128/CYNSE70256, IRST_L input to
the CYNCP80192 needs to be asserted for at least (0.5ms+64
CLK2X) cycles, while the clock is running and both
CYNCP80192
supplies are stable.
In order to reset CYNSE70032/CYNSE70064A, IRST_L input
to the CYNCP80192 needs to be asserted for at least (64
CLK2X) cycles, while the clock is running and both
CYNCP80192 and CYNSE70032/CYNSE70064A voltage
supplies are stable.
Hardware Interface Timing Protocols—NDC Interface. The
network processor interface of the NDC supports a variety of
SSRAM interfaces. It supports both SyncBurst as well as
NoBL SSRAMs. IFC_CFG[2:0] pins select the interface type
for the device as follows. (Refer to SSRAM specifications and
application notes from such vendors as Cypress and Micron.)
9.0
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2,
CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled two cycles later; for Read cycles, the data is
available to the processor two cycles later. Both Write- and
Read-cycle latency is two cycles and there is no gap required
between Read and Write operations. Every cycle is available
for the network processor(s) for full utilization of the bus
bandwidth. See Figure 9-1. Note. BWE_L is not used in this
mode and should be tied inactive.
• CLK2X output follows CLK input to the CYNCP80192.
• PHS_L is LOW when IRST_L is LOW. Otherwise, PHS_L
runs at half the speed of CLK.
000: NoBL pipelined mode
001: NoBL flowthrough mode
010: SyncBurst pipelined mode (early Write)
011: SyncBurst pipelined mode (late Write)
100–111: Reserved.
NoBL Pipelined SSRAM Interface Mode
and CYNSE70128/CYNSE70256 voltage
CYNCP80192
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