CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 27

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

Table 16-3. Operating Conditions
Table 16-4. AC Timing Parameters for Pipelined NoBL SSRAM and SyncBurst SSRAM
Table 16-5. AC Timing Parameters for NoBL and Flow-Through SSRAM
Document #: 38-02043 Rev. *C
V
V
V
V
T
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Notes:
13. Maximum allowable applies to overshoot only (V
14. Minimum allowable applies to undershoot only.
15. 1. T
16. 2. Set-up time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable.
17. 3. Hold time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable.
Parameter
A
DDQ
DD
IH
IL
CLK
CKHI
CKLO
SA
HA
CKOV
CK2X
CLKPHSL
CKSE
SCK
CKSD
CKOLZ
CKOHZ
CLK
CKHI
CKLO
SA
HA
CKOV
CLK2
CLKPHSL
CKSE
SCK
CKSD
CKOLZ
CKOHZ
Parameter
CLKHI
and T
CLK period: max frequency
CLK high pulse; worst-case 40%–60% duty cycle
CLK low pulse; worst-case 40%–60% duty cycle
Set-up Time to CLK rising edge
Hold Time to CLK rising edge
Clock to output valid (Network Processor
Interface)
Clock to CLK2X delay
Clock to PHS_L delay
Clock to output valid (NSE Interface)
Clock to SCLK delay
Clock to output valid (SDATA)
Clock to output in Low-Z
Clock to output in High-Z
CLK period: max frequency
CLK high pulse; worst-case 40%–60% duty cycle
CLK low pulse; worst-case 40%–60% duty cycle
Address setup time to CLK rising edge
Address hold time to CLK rising edge
Clock to output valid (network processor interface)
Clock to CLK2X delay
Clock to PHS_L delay
Clock to output valid (NSE Interface)
Clock to SCLK delay
Clock to output valid (SDATA)
Clock to output in low-Z
Clock to output in high-Z
CLKO
Operating Voltage for IO
Operating Supply Voltage
Input High Voltage
Input Low Voltage
Ambient Operating Temperature
Supply Voltage Tolerance
duty-cycle values are based on 20–80% signal levels.
Description
Description
Description
[14]
[13]
[17]
DDQ
[16]
is 3.3V supply).
[15]
[15]
Test Conditions
Load (pF)
30
40
20
Min.
–5%
3.14
2.37
–0.3
2.0
0
Test Conditions
Load (pF)
30
40
20
CYNPC80192–100 CYNPC80192–83
Min.
4.0
4.0
2.5
1.5
V
3
DD
Max.
3.45
2.63
+5%
0.8
70
+ 0.3
Max.
100
8.0
3.5
10
6
9
5
6
CYNPC80192–83
Min
8
8
6
2
3
Min.
CYNCP80192
4.8
4.8
3.0
1.5
3
Max
50
18
12
13
4
7
6
7
Unit
°C
Page 27 of 37
V
V
V
V
Max.
9.0
4.0
83
11
12
7
6
7
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Unit
Ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns