CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 23

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

DATA[63:0]
12.0
Mode (Late Write)
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2,
CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled one cycle later; for Read cycles, the data is
available to the processor one cycle later. Both Write- and
13.0
There are two ways to build a database coprocessing
subsystem
SSRAMs. In the first system the associative data SSRAMs are
connected to the coprocessor and the NSE (Figure 13-1) and
the coprocessor returns the associated data in response to a
search operation. This type of implementation is suited to
applications where the associative data size is up to eight
bytes.
Document #: 38-02043 Rev. *C
BW_L[7:0]
CPID[7:0]
ADR[9:0]
R/W_L
STRB
CE_L
CE_2
CLK
SyncBurst Pipelined SSRAM Interface
Application Information
using
CYNPC80192,
1
Write
A1
Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write)
Figure 13-1. Configuration 1—Associative SSRAM Mode
2
Read
D1
CYNSE70XXX,
A2
Coprocessor
3
NOP
and
4
Q2
A3
Read-cycle latency is one cycle, and there is no gap required
between Read and Write operation. Every cycle is available
for the network processor(s) for full utilization of the bus
bandwidth. See Figure 12-1. Note. BWE_L is not used in this
mode and should be tied inactive.
CPID
5
D3
Write
A4
Bank
NSE
6
Read
A5
7
SSRAM
Bank
Q4
8
CYNCP80192
Q5
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