CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 9

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. Search Coprocessor Pin Description (continued)
5.0
The CYNPC80192 receives up to a 100-MHz master CLK at
the coprocessor interface. The CYNPC80192 then generates
the CLK2X and a phase signal PHS_L for the NSEs, and the
SCLK for the associative data SSRAMs, as shown in
Figure 5-1.
6.0
6.1
The network processor(s) access the NDC using the
coprocessor (SSRAM) interface. The NDC has a CFG and
status registers area and an operating registers area, as
shown in Table 6-1.
Table 6-1. Register Partitions for Coprocessor Access
Note:
Document #: 38-02043 Rev. *C
4.
Test Access Port
Parameter
CLK for SSRAMs
ADR[9] = 1
The resulting registers of the context descriptors are Read-only.
TRST_L
512–1023
Address
TDO
TMS
TCK
CYNPC80192
0–511
TDI
Input signals
Input CLK to
Coprocessor Interface Register
Clocks
Registers
for NSEs
CFG and Status
Registers
Operating Registers
Type
CLK2X
PHS_L
T
I
I
I
I
SCLK
Abbreviation
CLK
IEEE 1149 JTAG test data in.
IEEE 1149 JTAG test clock.
IEEE 1149 JTAG test data out.
IEEE 1149 JTAG test mode select.
IEEE 1149 JTAG reset.
Type
R/W
R/W
Figure 5-1. NDC Clocks
These registers are for configuring the NDC (Read/Write), reporting the
error code in the status register (Read-only), setting up the mask register
for asserting INTR (Read/Write), and obtaining information on the device
(Read-only).
Dynamic access for searches and table management happens through this
area of the coprocessor address space.
Description
Description
[4]
CYNCP80192
Page 9 of 37